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AgeCommit message (Expand)AuthorFilesLines
2019-11-11rvv: refine vsetvl[i] logicChih-Min Chao1-4/+17
2019-10-24Initialize histogram_enabled and log_commits_enabled in constructor (#354)Scott Johnson1-0/+1
2019-09-18Adds --log-commits commandline option. (#323)dave-estes-syzexion1-0/+13
2019-08-23Remove statement with no effectAndrew Waterman1-1/+0
2019-07-19Set vtype.vill correctly; also reset it to trueAndrew Waterman1-3/+8
2019-07-19Check presence of V extension when accessing vector CSRsAndrew Waterman1-0/+15
2019-07-19VL and VTYPE aren't writable CSRsAndrew Waterman1-12/+0
2019-07-16Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)Tim Newsome1-2/+7
2019-07-12Add debug_mode state bit, rather than overloading dcsr.causeAndrew Waterman1-4/+5
2019-07-11Fix support for 32-bit hosts (but no V extension in that case!)Andrew Waterman1-1/+5
2019-07-11Support S-mode vectored interruptsAndrew Waterman1-2/+3
2019-07-05Fix clang uninitialized variable warningAndrew Waterman1-1/+1
2019-06-18rvv: add control instructions and system register accessChih-Min Chao1-0/+31
2019-06-14rvv: add varch option parser and initialize vector unitChih-Min Chao1-4/+67
2019-06-14rvv: add vector unit structureChih-Min Chao1-0/+26
2019-03-30RV32Q is not invalidAndrew Waterman1-3/+0
2019-03-27Respect interrupt priorities even when not delegatedAndrew Waterman1-9/+13
2019-02-04Fix use of old name `riscv-isa-run` (#269)Luís Marques1-1/+1
2018-12-21Reserve the PMP R=0 W=1 combinationAndrew Waterman1-2/+5
2018-10-04Set marchid to assigned value 5Andrew Waterman1-1/+1
2018-09-27Add comment about CSR read side effectsAndrew Waterman1-0/+3
2018-09-25For backwards compatibility, reset PMP to permit all accessesAndrew Waterman1-0/+3
2018-09-25Add PMP supportAndrew Waterman1-0/+32
2018-08-22Make IRQ_COP read-only/undelegable unless coprocessor is presentAndrew Waterman1-1/+2
2018-08-21Instantiate disassembler after max_xlen is knownAndrew Waterman1-1/+5
2018-08-17Don't increment instret immediately after it is written (#231)Andrew Waterman1-0/+6
2018-07-31Make sstatus.MXR readableAndrew Waterman1-1/+1
2018-07-23Fix using the uninitialized disassemble object. (#220)SeungRyeol Lee1-1/+1
2018-07-10Refactor and fix LR/SC implementation (#217)Andrew Waterman1-3/+0
2018-05-31Put simif_t declaration in its own file. (#209)Andy Wright1-1/+1
2018-03-21Implement Hauser misa.C misalignment proposal (#187)Andrew Waterman1-3/+7
2018-03-19Fix spike-dasm. (#184)Tim Newsome1-1/+2
2018-03-16Implement debug havereset bitsTim Newsome1-0/+2
2018-03-14Fix a bug caused by moving misa into state_t. (#180)Prashanth Mundkur1-2/+3
2018-03-13Move processor.isa to state.misa, since it really belongs there.Prashanth Mundkur1-8/+8
2018-03-06Narrow the interface used by the processors and memory to the top-level simul...Prashanth Mundkur1-1/+1
2018-03-03Enforce 2-byte alignment of mepc/sepc/dpcAndrew Waterman1-3/+3
2018-02-13Implement cycleh/instreth CSRs for RV32 (#172)Andrew Waterman1-0/+5
2017-11-27Rename badaddr to tvalAndrew Waterman1-9/+9
2017-11-27Rename sptbr to satpAndrew Waterman1-8/+8
2017-11-27Set tval to 0 on traps with no specified tvalAndrew Waterman1-4/+2
2017-11-20Implement priv-1.11 interrupt-priority scheme (#161)Andrew Waterman1-1/+18
2017-11-09Remove redundant U/S mode advertisementAndrew Waterman1-4/+0
2017-11-09H-mode no longer existsAndrew Waterman1-1/+0
2017-11-09MPP is now WARLAndrew Waterman1-6/+22
2017-11-02Mask medeleg correctlyAndrew Waterman1-3/+7
2017-11-01Don't permit delegation of interrupts that M-mode should handleAndrew Waterman1-4/+3
2017-09-28Implement Q extensionAndrew Waterman1-2/+8
2017-09-21Fix corner case in repeated execution (#127)Tim Newsome1-4/+1
2017-09-12Don't take interrupts while in Debug Mode.Tim Newsome1-1/+1
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