Age | Commit message (Collapse) | Author | Files | Lines | |
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2019-07-22 | Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311) | Tim Newsome | 1 | -1/+6 | |
* Don't corrupt s0 when abstract CSR write fails. * Support abstract FPR access then mstatus.FS=0 Discussion on the spec list leans towards this being a requirement. Certainly users want their debugger to be able to access all registers regardless of target state. | |||||
2019-05-13 | Revert "Add FLH and FSH instructions expanding IEEE fp16 in memory to fp32 ↵ | Chih-Min Chao | 1 | -19/+0 | |
in registers" this is experimental implementation This reverts commit f04f29d352d413d2bc1ed1c7f60319461746540a. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-01-21 | Add FLH and FSH instructions expanding IEEE fp16 in memory to fp32 in registers | Bruce Hoult | 1 | -0/+19 | |
2017-02-15 | Implement resume (untested). | Tim Newsome | 1 | -0/+3 | |
2017-02-10 | Entering debug mode now jumps to "dynamic rom" | Tim Newsome | 1 | -0/+241 | |
2013-11-25 | Update to new privileged ISA | Andrew Waterman | 1 | -158/+0 | |
2013-11-21 | fix slli/slliw encoding bug | Yunsup Lee | 1 | -2/+2 | |
2013-09-21 | Update ISA encoding and AUIPC semantics | Andrew Waterman | 1 | -156/+154 | |
2013-09-15 | ISA changes | Andrew Waterman | 1 | -2/+2 | |
2013-09-11 | Add AMOXOR | Andrew Waterman | 1 | -16/+18 | |
2013-09-11 | Implement zany immediates | Andrew Waterman | 1 | -6/+6 | |
2013-09-10 | Add rd field to JAL; drop J | Andrew Waterman | 1 | -26/+25 | |
2013-08-08 | Rename MTFSR/MFFSR to FSSR/FRSR | Andrew Waterman | 1 | -2/+2 | |
2013-08-08 | Swap J and JALR encoding | Andrew Waterman | 1 | -2/+2 | |
2013-07-26 | New supervisor mode | Andrew Waterman | 1 | -5/+5 | |
2013-07-26 | Rename MFTX/MXTF to FMV | Andrew Waterman | 1 | -4/+4 | |
2013-07-26 | Rip out Hwacha for now | Andrew Waterman | 1 | -89/+0 | |
2013-07-26 | Rip out RVC for now | Andrew Waterman | 1 | -34/+0 | |
2013-07-25 | Remove JALR static hints | Andrew Waterman | 1 | -13/+10 | |
2013-04-17 | add AUIPC insn; remove RDNPC insn | Andrew Waterman | 1 | -2/+2 | |
2013-03-29 | add load-reserved/store-conditional instructions | Andrew Waterman | 1 | -2/+6 | |
2013-03-27 | opcodes.h must only contain DECLARE_INSN() lines | Andrew Waterman | 1 | -2/+0 | |
2013-03-25 | add BSD license | Andrew Waterman | 1 | -0/+2 | |
2012-03-24 | new supervisor mode | Andrew Waterman | 1 | -17/+16 | |
2012-03-18 | update vector fences | Andrew Waterman | 1 | -8/+6 | |
2012-03-18 | clean up vector exception instructions | Yunsup Lee | 1 | -8/+10 | |
2012-03-13 | add more instructions for vector exception handling | Yunsup Lee | 1 | -4/+7 | |
2012-03-13 | add vvcfg,vtcfg | Yunsup Lee | 1 | -1/+3 | |
2012-03-13 | opcodes cleanup | Yunsup Lee | 1 | -8/+7 | |
2012-03-10 | slight change to vector supervisor instructions | Yunsup Lee | 1 | -4/+4 | |
2012-03-03 | new instructions to handle vector exceptions | Yunsup Lee | 1 | -0/+6 | |
2011-11-11 | Changed MFTX to use rs1 for its source | Andrew Waterman | 1 | -2/+2 | |
2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+272 | |
2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -272/+0 | |
2011-06-10 | [sim, opcodes] made sim more decoupled from opcodes | Andrew Waterman | 1 | -0/+272 | |