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It's very difficult to encounter this (need to manually place a device or
memory at very high addresses), but it is technically a Spike bug.
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* Extends the commit log feature with memory writes.
This provides a little more information for debugging instruction
traces, allowing you to maintain the state of memory as the trace
is processed.
The following sample trace output illustrates the formatting of
the new memory writes. The first line is an instruction at
location 0x80000094, containing the bytes (0x80830313) and
commiting the value 0x80000898 to the register x6. The second
line is an instruction which neither commits a register nor
writes memory. The third line writes the value 0x0 to
0x80000890.
3 0x80000094 (0x80830313) x 6 0x80000898
3 0x80000098 (0x0062d663)
3 0x8000009c (0x00028023) mem 0x80000890 0x0
* Changes addressing feedback from review.
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PMP checks should unconditionally fail if the PMP matches part of, but
not all of, an access. We got this right, but went too far: we checked
whether _any_ PMP matches in this manner. In fact, only the first PMP
that maches any of the bytes should be checked in this manner.
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1. When hitting a trigger during a single step, dcsr.cause must reflect
the trigger not the step.
2. Also check for triggers on accesses that require a slow path fetch.
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- Use physical addresses to avoid homonym ambiguity (closes #215)
- Yield reservation on store-conditional (https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612)
- Don't yield reservation on exceptions (it's no longer required).
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By separating the simif_t declaration from the sim_t declaration, the
simif_t declaration no longer depends on fesvr header files. This
simplifies compilation of custom sim class implementations that don't
depend on fesvr.
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simulator/htif.
This allows the implementation of an alternative top-level simulator class.
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I$ indices now maintain a 1:N relationship with PCs. This is somewhat
faster and also simpler.
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Resolves #93
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https://github.com/riscv/riscv-isa-manual/issues/4
Also, refactor gdbserver code to not duplicate VM decoding logic.
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This commit also factors out the common AMO code into mmu_t.
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So far I only have testcases for instruction and data address.
Not implemented is the mechanism that lets the debugger prevent a user
program from using triggers at all. I'll be adding that soonish.
The critical path is unchanged, but my experimenting shows the
simulation is slowed down about 8% by this code. Reducing the size of
trigger_match() (which is never called during my benchmark) fixes that,
but making it not be inlined has no effect. I suspect the slowdown comes
from cache alignment or something similar, and on a different CPU or
after more code changes the speed will come back.
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This avoids the need for fence.i.
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This replaces a hack that just disabled all of the icache.
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(gdb) target remote localhost:1234
Remote debugging using localhost:1234
0x0000000000010178 in fib (n=0) at waste.c:1
1 unsigned int fib(unsigned int n) {
(gdb)
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This should replace the ROM hack I implemented earlier, but for now both
exist together.
Back to the point where gdb connects, core jumps to ROM->RAM->ROM.
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Reset vector is at 0x1000; below that is reserved for debug
Memory is at 0x80000000
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Of course, it doesn't do anything yet.
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- Performance for variable-length instructions is much better
- Refill is simpler and faster
- Support for instructions with overlapping opcodes (e.g. C.ADD + C.JALR)
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Also, improve performance by allowing the soft-ITLB to refill.
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Default is RV64IMAFDC. Can do things like
--isa=RV32 (which implies IMAFDC)
--isa=IM (which implies RV64)
--isa=RV64IMAFDXhwacha
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In particular, precompiled headers ideally won't depend on any.
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Most of the complexity is in instruction address translation, since
instructions may span page boundaries.
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We now use a heavily unrolled loop as the software I$, which allows the
host machine's branch target prediction to associate target PCs with
unique-ish host PCs.
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