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The scheme was based on the notion that memory accesses are idempotent
up until the point the trigger would've been hit, which isn't true in
the case of side-effecting loads and data-value triggers.
Instead, check the trigger on the next instruction fetch. To keep the
perf overhead minimal, perform this check on the I$ refill path, and
ensure that path is taken by flushing the I$.
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As a side effect, misaligned stores now behave the same as aligned stores
with respect to triggers: only the first byte is checked.
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As a side effect, misaligned loads now behave the same as aligned loads
with respect to triggers: only the first byte is checked.
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Fix trigger priority
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The spec defines that the mcontrol store address/data has a higher
priority over page fault and address misalignment (Debug spec, Table
5.2). Thus, the trigger checking should be before the translation and
alignment checking.
The previous implementation checks the trigger after the translation and
alignment, resulting in incorrect priority. For instance, when page fault
and trigger occur on the same instruction, the previous implementation
will choose to raise the page fault, which contradicts the priority
requirement.
This commit moves the trigger checking before the misaligned checking and
translation. The trigger will fire on the instruction instead of the page
fault in the above case.
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The spec defines the mcontrol load address has a higher priority over
page fault and address misaligned (Debug spec, Table 5.2). Thus, the
trigger checking should be before the translation and alignment
checking.
The previous implementation checks the trigger after the translation
and alignment, resulting in incorrect priority. For instance, when page
fault and trigger occur on the same instruction, the previous
implementation will choose to raise the page fault, which contradicts
the priority requirement.
This commit adds an address-only trigger checking before the misaligned
checking and translation. The trigger will fire on the instruction
instead of the page fault in the above case.
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The spec defines the mcontrol execute address has a higher priority over
page fault (Debug spec, Table 5.2). Thus, the trigger checking should be
before the translation.
The previous implementation checks the trigger after the translation,
resulting in incorrect priority. For instance, when page fault and
trigger occur on the same instruction, the previous implementation will
choose to raise the page fault, which contradicts the priority
requirement.
This commit adds an address-only trigger checking before the
translation. The trigger will fire on the instruction instead of the
page fault in the above case.
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The mcontrol trigger can select either address or data for checking. The
The selection decides the priority of the trigger. For instance, the
address trigger has a higher priority over the page fault, and the page
fault has a higher priority over the data trigger.
The previous implementation only has the checking functions for data
trigger, which results in incorrect priority of address trigger.
This commit adds a has_data argument to indicate address trigger and the
priority of the trigger.
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The trigger matching only checks on TLB hit (after refill_tlb()).
However, instructions on plugin devices will never be filled into
the TLB; thus, triggers cannot fire when executing instructions on
the plugin devices.
The PR removes the if-condition of TLB hit for trigger checking.
Co-authored-by: Howard Yen-Hao Chen <yhchen@andestech.com>
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Because it's always better to do so where possible.
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No reason to use a variable misleadingly named 'paddr' to hold the
virtual address.
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Hopefully for the last time :-)
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It was accessing memory using the current privilege mode instead of
the expected guest privilege.
Once #872 is fixed, I suspect we can greatly simplify this.
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They were accessing memory using the current privilege mode instead of
the expected guest privilege.
Once #872 is fixed, I suspect we can greatly simplify this.
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It was previously necessary because we were shifting left before
assigning to a reg_t, but that changed in the previous commit.
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Since the last step is about to get much more complex
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Since the middle step is about to get much more complex
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...since we no longer rely on their being sign-extended.
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In future, someone may expect this functionality.
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Is passed along to the contained store_func.
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Will be used similarly as in load_func.
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Didn't want to make change in previous commit to isolate the change.
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start of AMO.
This includes skipping store in store_slow_path.
Is okay to skip the mmio_store part too, since the access_fault for mmio_failure will be caught on the actual store.
The ordering for the mmio_access fault is irrelevant since it will occur after the TW faults, and load faults are converted to store faults.
Will catch any faults from the access but won't perform a store.
Since store permissions can only be granted if read permissions exist,
any store faults will occur before or at the same time as a load fault.
Thus this store permissions check is sufficient for properly catching the faults in an Amo access TW.
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Will be used to check store attributes without actually performing the store.
Needed to AMO bug fix.
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Refactor trigger code
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Created a new triggers::module_t to hold the structure.
Also make sure mcontrol_t instances are properly initialized.
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prefetch.* are hints and share the encoding of ORI with rd = 0. so it can share the implementation of ORI and execute as no-ops
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Since that's what it was returning anyway.
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When V=1, vsstatus.MXR applies to the first stage of translation,
and mstatus.MXR applies to both.
mstatus.SUM doesn't apply when V=1, but vsstatus.SUM does.
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It should require X permissions, rather than (R || X).
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The previous scheme flushed the TLB before and after HLV/HSV. I think
this was slightly wrong in the case of a debug trigger match: because
the TLB gets refilled before the trigger exception gets thrown, we might
not have reached the second TLB flush, so the entry could linger.
Instead of flushing, simply don't access the TLB and don't refill the
TLB for these instructions. Other than the trigger exception case,
the effect is the same: we'll perform a full table walk and we won't
cache the result.
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It has been discussed that mis-aligned exception needs to update mstata.GVA
ref:
https://github.com/riscv/riscv-isa-manual/issues/673
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Co-authored-by: zhongchengyong <zhongcy93@gmail.com>
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Co-authored-by: zhongcy <zhongcy93@gmail.com>
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