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2022-04-11Merge pull request #944 from riscv-software-src/triggersScott Johnson1-25/+15
2022-04-05Move trigger match logic into triggers.ccTim Newsome1-8/+10
2022-04-05module_t::trigger_match -> memory_access_matchTim Newsome1-2/+2
2022-04-05trigger_matched_t -> triggers::matched_tTim Newsome1-18/+5
2022-04-05Give triggers::module_t its own processor_t*Tim Newsome1-2/+2
2022-04-05Move trigger_match() into triggers.Tim Newsome1-2/+2
2022-03-30Replace state.mcontrol with TM.triggers.Tim Newsome1-1/+1
2022-03-30trigger_operation_t -> triggers::operation_tTim Newsome1-7/+8
2022-03-30Implement Sv57 and Sv57x4 translation modesAndrew Waterman1-0/+1
2022-01-30add instructions function for cmoliweiwei1-14/+36
2022-01-29add blocksz parameter to specify the cache block size for CBO operationsliweiwei1-0/+6
2021-09-08Make pmp_ok return type boolScott Johnson1-1/+1
2021-07-21Fix hypervisor MXR and SUMAndrew Waterman1-2/+2
2021-07-21Fix HLVX permissions checkAndrew Waterman1-5/+5
2021-07-21Simplify (and possibly fix) handling of HLV/HSV TLB accessesAndrew Waterman1-12/+4
2021-07-17ext-h: handle mis-aligned exception for guest worldChih-Min Chao1-16/+20
2021-06-12Revert the redundant check for lr instruction (#728)sven1-4/+1
2021-05-25Add alignment check for lr instruction (#713)sven1-1/+4
2021-03-02Fix AMO guest page fault as store guest fault (#663)francis40961-0/+3
2021-02-04Fix compile errorsAndrew Waterman1-4/+4
2021-01-20add support to page on demand (#634)Chih-Min Chao1-0/+3
2020-12-18If misaligned accesses are enabled, throw access fault on misaligned LR/SCAndrew Waterman1-2/+20
2020-12-18Check and use proc variable in MMU emulationAnup Patel1-2/+2
2020-11-27Fix hstatus.GVA and mstatus.GVA updationAnup Patel1-4/+4
2020-11-23Fix misaligned loads and stores for big endian target (#602)Marcus Comstedt1-2/+2
2020-11-12Correct AMO exception cause for misaligned accesses (#594)Scott Johnson1-0/+3
2020-11-11Use new require_alignment flag to simplify AMO checkScott Johnson1-3/+1
2020-11-11Make LR properly take misaligned exceptionScott Johnson1-4/+6
2020-11-07Make mmu_t::target_big_endian always availableMarcus Comstedt1-12/+2
2020-11-07Tag target endian values to help guide conversion codeMarcus Comstedt1-13/+13
2020-11-07Implement support for big-endian targetsMarcus Comstedt1-9/+48
2020-10-24Fix trap generation in s2xlate()Anup Patel1-1/+1
2020-07-09Implement hypervisor two-stage MMUAnup Patel1-36/+84
2020-07-08Extend trap classes to pass more informationAnup Patel1-10/+10
2020-06-08Fix priority of misaligned exceptions for store-conditionalAndrew Waterman1-1/+4
2020-03-23commitlog: fix wrong dump when exception occursChih-Min Chao1-1/+1
2020-02-20Disallow access to debug memory region unless in debug modeAndrew Waterman1-0/+3
2020-01-13commitlog: extend load/store record to keep multiple accessChih-Min Chao1-9/+4
2019-12-16extend the commit and memory writes log feature with memory reads (#370)John Ingalls1-6/+21
2019-10-28Implement support for big-endian hostsMarcus Comstedt1-16/+19
2019-10-16Enforce 2^56-bit physical address limitAndrew Waterman1-0/+1
2019-09-18Extends the commit log feature with memory writes. (#324)dave-estes-syzexion1-1/+15
2019-01-28Fix PMP checks for partially-matching accesses (#270)Andrew Waterman1-1/+1
2018-09-25Add PMP supportAndrew Waterman1-3/+6
2018-08-10Fix 2 trigger corner cases. (#229)Tim Newsome1-3/+9
2018-07-10Refactor and fix LR/SC implementation (#217)Andrew Waterman1-0/+24
2018-05-31Put simif_t declaration in its own file. (#209)Andy Wright1-1/+1
2018-04-04Allow querying the mmu configuration chosen during the build. (#191)Prashanth Mundkur1-0/+18
2018-03-06Narrow the interface used by the processors and memory to the top-level simul...Prashanth Mundkur1-2/+2
2018-02-21Don't allow 32-bit instructions to take up multiple slots in I$Andrew Waterman1-1/+2
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