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riscv
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mmu.h
Age
Commit message (
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Author
Files
Lines
2015-09-24
Refactor memory access code; add MMIO support
Andrew Waterman
1
-36
/
+38
2015-09-24
Use enum instead of two bools to denote memory access type
Andrew Waterman
1
-19
/
+21
2015-09-08
Improve instruction fetch
Andrew Waterman
1
-15
/
+15
2015-07-10
fix clang compile error
Scott Beamer
1
-0
/
+1
2015-04-25
Fix I$ simulator hit count
Andrew Waterman
1
-4
/
+5
2015-04-03
Support setting ISA/subsets with --isa flag
Andrew Waterman
1
-7
/
+2
2015-03-30
Implement RVC draft
Andrew Waterman
1
-12
/
+11
2015-03-26
New virtual memory implementation (Sv39)
Andrew Waterman
1
-4
/
+3
2015-03-14
Don't set dirty/referenced bits w/o permission
Andrew Waterman
1
-1
/
+1
2015-03-12
Implement PTE referenced/dirty bits
Andrew Waterman
1
-2
/
+2
2015-01-02
Require 4-byte instruction alignment until RVC is reimplemented
Andrew Waterman
1
-1
/
+2
2015-01-02
On misaligned fetch, set EPC to target, not branch itself
Andrew Waterman
1
-1
/
+3
2015-01-02
Reduce dependences on auto-generated code
Andrew Waterman
1
-3
/
+4
2014-12-04
Support 2/4/6/8-byte instructions
Andrew Waterman
1
-13
/
+32
2014-02-13
Fix I$ simulator not making forward progress
Andrew Waterman
1
-5
/
+5
2014-01-13
Improve performance for branchy code
Andrew Waterman
1
-35
/
+39
2013-12-17
Speed things up quite a bit
Andrew Waterman
1
-31
/
+40
2013-09-11
Implement zany immediates
Andrew Waterman
1
-8
/
+11
2013-08-11
Instructions are no longer member functions
Andrew Waterman
1
-25
/
+2
2013-07-28
Don't flush TLB on PTBR writes (only FATC)
Andrew Waterman
1
-1
/
+1
2013-07-26
New supervisor mode
Andrew Waterman
1
-17
/
+3
2013-07-26
Remove more vector stuff
Andrew Waterman
1
-3
/
+0
2013-07-26
Rip out RVC for now
Andrew Waterman
1
-42
/
+17
2013-07-26
Generate instruction decoder dynamically
Andrew Waterman
1
-22
/
+18
2013-03-29
add load-reserved/store-conditional instructions
Andrew Waterman
1
-2
/
+13
2013-03-25
add BSD license
Andrew Waterman
1
-0
/
+2
2013-03-25
truncate effective addresses in rv32
Andrew Waterman
1
-11
/
+4
2013-02-15
don't store host pointers in soft TLB
Andrew Waterman
1
-15
/
+18
2013-02-13
clean up fetch-execute loop a bit
Andrew Waterman
1
-28
/
+32
2013-02-13
add I$/D$/L2$ simulators
Andrew Waterman
1
-15
/
+23
2012-01-24
check that virtual addresses are sign-extended
Andrew Waterman
1
-0
/
+2
2012-01-22
disentangle decode.h from other headers
Andrew Waterman
1
-0
/
+1
2011-11-01
Fixed tight coupling of host and target page size
Andrew Waterman
1
-1
/
+1
2011-10-27
changed page size to 8KB
Andrew Waterman
1
-4
/
+3
2011-06-19
temporary undoing of renaming
Andrew Waterman
1
-0
/
+191
2011-06-12
[sim] renamed to riscv-isa-run
Andrew Waterman
1
-194
/
+0
2011-06-12
[xcc] minor performance tweaks
Andrew Waterman
1
-4
/
+13
2011-06-11
[xcc] tlb now stores host addresses
Andrew Waterman
1
-16
/
+16
2011-06-11
[xcc] cleaned up mmu code
Andrew Waterman
1
-96
/
+26
2011-05-31
[sim] fault on failed addr translations
Andrew Waterman
1
-1
/
+21
2011-05-31
[sim] minor sim cleanup
Andrew Waterman
1
-16
/
+6
2011-05-29
[sim,opcodes] improved sim build and run performance
Andrew Waterman
1
-50
/
+44
2011-05-28
[fesvr,xcc,sim] fixed multicore sim for akaros
Andrew Waterman
1
-14
/
+23
2011-05-16
[sim,pk] cleanups & initial virtual memory support
Andrew Waterman
1
-38
/
+46
2011-05-13
[sim] initial support for virtual memory
Andrew Waterman
1
-17
/
+126
2011-05-06
[sim] fixed building sim without cache simulators
Andrew Waterman
1
-1
/
+1
2011-04-30
[sim] hacked in a dcache simulator
Andrew Waterman
1
-1
/
+33
2011-04-15
[sim] added icache simulator (disabled by default)
Andrew Waterman
1
-0
/
+9
2011-04-12
[sim,pk] fixed minor pk bugs and trap codes
Andrew Waterman
1
-3
/
+5
2011-04-11
[xcc,sim,opcodes] more rvc instructions and bug fixes
Andrew Waterman
1
-3
/
+1
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