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mmu.h
Age
Commit message (
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Author
Files
Lines
2021-09-08
Make pmp_ok return type bool
Scott Johnson
1
-1
/
+1
2021-07-21
Fix hypervisor MXR and SUM
Andrew Waterman
1
-2
/
+2
2021-07-21
Fix HLVX permissions check
Andrew Waterman
1
-5
/
+5
2021-07-21
Simplify (and possibly fix) handling of HLV/HSV TLB accesses
Andrew Waterman
1
-12
/
+4
2021-07-17
ext-h: handle mis-aligned exception for guest world
Chih-Min Chao
1
-16
/
+20
2021-06-12
Revert the redundant check for lr instruction (#728)
sven
1
-4
/
+1
2021-05-25
Add alignment check for lr instruction (#713)
sven
1
-1
/
+4
2021-03-02
Fix AMO guest page fault as store guest fault (#663)
francis4096
1
-0
/
+3
2021-02-04
Fix compile errors
Andrew Waterman
1
-4
/
+4
2021-01-20
add support to page on demand (#634)
Chih-Min Chao
1
-0
/
+3
2020-12-18
If misaligned accesses are enabled, throw access fault on misaligned LR/SC
Andrew Waterman
1
-2
/
+20
2020-12-18
Check and use proc variable in MMU emulation
Anup Patel
1
-2
/
+2
2020-11-27
Fix hstatus.GVA and mstatus.GVA updation
Anup Patel
1
-4
/
+4
2020-11-23
Fix misaligned loads and stores for big endian target (#602)
Marcus Comstedt
1
-2
/
+2
2020-11-12
Correct AMO exception cause for misaligned accesses (#594)
Scott Johnson
1
-0
/
+3
2020-11-11
Use new require_alignment flag to simplify AMO check
Scott Johnson
1
-3
/
+1
2020-11-11
Make LR properly take misaligned exception
Scott Johnson
1
-4
/
+6
2020-11-07
Make mmu_t::target_big_endian always available
Marcus Comstedt
1
-12
/
+2
2020-11-07
Tag target endian values to help guide conversion code
Marcus Comstedt
1
-13
/
+13
2020-11-07
Implement support for big-endian targets
Marcus Comstedt
1
-9
/
+48
2020-10-24
Fix trap generation in s2xlate()
Anup Patel
1
-1
/
+1
2020-07-09
Implement hypervisor two-stage MMU
Anup Patel
1
-36
/
+84
2020-07-08
Extend trap classes to pass more information
Anup Patel
1
-10
/
+10
2020-06-08
Fix priority of misaligned exceptions for store-conditional
Andrew Waterman
1
-1
/
+4
2020-03-23
commitlog: fix wrong dump when exception occurs
Chih-Min Chao
1
-1
/
+1
2020-02-20
Disallow access to debug memory region unless in debug mode
Andrew Waterman
1
-0
/
+3
2020-01-13
commitlog: extend load/store record to keep multiple access
Chih-Min Chao
1
-9
/
+4
2019-12-16
extend the commit and memory writes log feature with memory reads (#370)
John Ingalls
1
-6
/
+21
2019-10-28
Implement support for big-endian hosts
Marcus Comstedt
1
-16
/
+19
2019-10-16
Enforce 2^56-bit physical address limit
Andrew Waterman
1
-0
/
+1
2019-09-18
Extends the commit log feature with memory writes. (#324)
dave-estes-syzexion
1
-1
/
+15
2019-01-28
Fix PMP checks for partially-matching accesses (#270)
Andrew Waterman
1
-1
/
+1
2018-09-25
Add PMP support
Andrew Waterman
1
-3
/
+6
2018-08-10
Fix 2 trigger corner cases. (#229)
Tim Newsome
1
-3
/
+9
2018-07-10
Refactor and fix LR/SC implementation (#217)
Andrew Waterman
1
-0
/
+24
2018-05-31
Put simif_t declaration in its own file. (#209)
Andy Wright
1
-1
/
+1
2018-04-04
Allow querying the mmu configuration chosen during the build. (#191)
Prashanth Mundkur
1
-0
/
+18
2018-03-06
Narrow the interface used by the processors and memory to the top-level simul...
Prashanth Mundkur
1
-2
/
+2
2018-02-21
Don't allow 32-bit instructions to take up multiple slots in I$
Andrew Waterman
1
-1
/
+2
2017-11-27
Rename badaddr to tval
Andrew Waterman
1
-2
/
+2
2017-11-27
Rename sptbr to satp
Andrew Waterman
1
-10
/
+10
2017-09-28
Implement Q extension
Andrew Waterman
1
-0
/
+19
2017-04-30
Store both host & target address in soft TLB
Andrew Waterman
1
-20
/
+29
2017-04-05
Add --enable-misaligned option for misaligned ld/st support
Andrew Waterman
1
-4
/
+26
2017-03-27
Separate page faults from physical memory access exceptions
Andrew Waterman
1
-0
/
+3
2017-02-08
Encode VM type in sptbr, not mstatus
Andrew Waterman
1
-0
/
+31
2016-11-13
Fix 32-bit host portability bug
Andrew Waterman
1
-1
/
+1
2016-11-10
AMOs should always return store faults, not load faults
Andrew Waterman
1
-0
/
+20
2016-09-02
Support triggers on TLB misses.
Tim Newsome
1
-0
/
+3
2016-09-01
Theoretically support trigger timing.
Tim Newsome
1
-0
/
+3
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