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path: root/riscv/mmu.h
AgeCommit message (Expand)AuthorFilesLines
2017-02-08Encode VM type in sptbr, not mstatusAndrew Waterman1-0/+31
2016-11-13Fix 32-bit host portability bugAndrew Waterman1-1/+1
2016-11-10AMOs should always return store faults, not load faultsAndrew Waterman1-0/+20
2016-09-02Support triggers on TLB misses.Tim Newsome1-0/+3
2016-09-01Theoretically support trigger timing.Tim Newsome1-0/+3
2016-08-22Implement address and data triggers.Tim Newsome1-0/+55
2016-07-06Update to new PTE formatAndrew Waterman1-1/+1
2016-06-22Don't use I$ in debug modeAndrew Waterman1-3/+4
2016-05-23Use fence.i in Debug ROM.Tim Newsome1-1/+0
2016-05-23gdb can attach and read the PC:Tim Newsome1-0/+1
2016-05-23Add debug_module bus device.Tim Newsome1-2/+4
2016-04-29Move much closer to new platform-M memory mapAndrew Waterman1-10/+6
2016-03-02implement PUM functionalityAndrew Waterman1-1/+1
2015-09-24Refactor memory access code; add MMIO supportAndrew Waterman1-36/+38
2015-09-24Use enum instead of two bools to denote memory access typeAndrew Waterman1-19/+21
2015-09-08Improve instruction fetchAndrew Waterman1-15/+15
2015-07-10fix clang compile errorScott Beamer1-0/+1
2015-04-25Fix I$ simulator hit countAndrew Waterman1-4/+5
2015-04-03Support setting ISA/subsets with --isa flagAndrew Waterman1-7/+2
2015-03-30Implement RVC draftAndrew Waterman1-12/+11
2015-03-26New virtual memory implementation (Sv39)Andrew Waterman1-4/+3
2015-03-14Don't set dirty/referenced bits w/o permissionAndrew Waterman1-1/+1
2015-03-12Implement PTE referenced/dirty bitsAndrew Waterman1-2/+2
2015-01-02Require 4-byte instruction alignment until RVC is reimplementedAndrew Waterman1-1/+2
2015-01-02On misaligned fetch, set EPC to target, not branch itselfAndrew Waterman1-1/+3
2015-01-02Reduce dependences on auto-generated codeAndrew Waterman1-3/+4
2014-12-04Support 2/4/6/8-byte instructionsAndrew Waterman1-13/+32
2014-02-13Fix I$ simulator not making forward progressAndrew Waterman1-5/+5
2014-01-13Improve performance for branchy codeAndrew Waterman1-35/+39
2013-12-17Speed things up quite a bitAndrew Waterman1-31/+40
2013-09-11Implement zany immediatesAndrew Waterman1-8/+11
2013-08-11Instructions are no longer member functionsAndrew Waterman1-25/+2
2013-07-28Don't flush TLB on PTBR writes (only FATC)Andrew Waterman1-1/+1
2013-07-26New supervisor modeAndrew Waterman1-17/+3
2013-07-26Remove more vector stuffAndrew Waterman1-3/+0
2013-07-26Rip out RVC for nowAndrew Waterman1-42/+17
2013-07-26Generate instruction decoder dynamicallyAndrew Waterman1-22/+18
2013-03-29add load-reserved/store-conditional instructionsAndrew Waterman1-2/+13
2013-03-25add BSD licenseAndrew Waterman1-0/+2
2013-03-25truncate effective addresses in rv32Andrew Waterman1-11/+4
2013-02-15don't store host pointers in soft TLBAndrew Waterman1-15/+18
2013-02-13clean up fetch-execute loop a bitAndrew Waterman1-28/+32
2013-02-13add I$/D$/L2$ simulatorsAndrew Waterman1-15/+23
2012-01-24check that virtual addresses are sign-extendedAndrew Waterman1-0/+2
2012-01-22disentangle decode.h from other headersAndrew Waterman1-0/+1
2011-11-01Fixed tight coupling of host and target page sizeAndrew Waterman1-1/+1
2011-10-27changed page size to 8KBAndrew Waterman1-4/+3
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+191
2011-06-12[sim] renamed to riscv-isa-runAndrew Waterman1-194/+0
2011-06-12[xcc] minor performance tweaksAndrew Waterman1-4/+13
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