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path: root/riscv/mmu.h
AgeCommit message (Expand)AuthorFilesLines
2015-07-10fix clang compile errorScott Beamer1-0/+1
2015-04-25Fix I$ simulator hit countAndrew Waterman1-4/+5
2015-04-03Support setting ISA/subsets with --isa flagAndrew Waterman1-7/+2
2015-03-30Implement RVC draftAndrew Waterman1-12/+11
2015-03-26New virtual memory implementation (Sv39)Andrew Waterman1-4/+3
2015-03-14Don't set dirty/referenced bits w/o permissionAndrew Waterman1-1/+1
2015-03-12Implement PTE referenced/dirty bitsAndrew Waterman1-2/+2
2015-01-02Require 4-byte instruction alignment until RVC is reimplementedAndrew Waterman1-1/+2
2015-01-02On misaligned fetch, set EPC to target, not branch itselfAndrew Waterman1-1/+3
2015-01-02Reduce dependences on auto-generated codeAndrew Waterman1-3/+4
2014-12-04Support 2/4/6/8-byte instructionsAndrew Waterman1-13/+32
2014-02-13Fix I$ simulator not making forward progressAndrew Waterman1-5/+5
2014-01-13Improve performance for branchy codeAndrew Waterman1-35/+39
2013-12-17Speed things up quite a bitAndrew Waterman1-31/+40
2013-09-11Implement zany immediatesAndrew Waterman1-8/+11
2013-08-11Instructions are no longer member functionsAndrew Waterman1-25/+2
2013-07-28Don't flush TLB on PTBR writes (only FATC)Andrew Waterman1-1/+1
2013-07-26New supervisor modeAndrew Waterman1-17/+3
2013-07-26Remove more vector stuffAndrew Waterman1-3/+0
2013-07-26Rip out RVC for nowAndrew Waterman1-42/+17
2013-07-26Generate instruction decoder dynamicallyAndrew Waterman1-22/+18
2013-03-29add load-reserved/store-conditional instructionsAndrew Waterman1-2/+13
2013-03-25add BSD licenseAndrew Waterman1-0/+2
2013-03-25truncate effective addresses in rv32Andrew Waterman1-11/+4
2013-02-15don't store host pointers in soft TLBAndrew Waterman1-15/+18
2013-02-13clean up fetch-execute loop a bitAndrew Waterman1-28/+32
2013-02-13add I$/D$/L2$ simulatorsAndrew Waterman1-15/+23
2012-01-24check that virtual addresses are sign-extendedAndrew Waterman1-0/+2
2012-01-22disentangle decode.h from other headersAndrew Waterman1-0/+1
2011-11-01Fixed tight coupling of host and target page sizeAndrew Waterman1-1/+1
2011-10-27changed page size to 8KBAndrew Waterman1-4/+3
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+191
2011-06-12[sim] renamed to riscv-isa-runAndrew Waterman1-194/+0
2011-06-12[xcc] minor performance tweaksAndrew Waterman1-4/+13
2011-06-11[xcc] tlb now stores host addressesAndrew Waterman1-16/+16
2011-06-11[xcc] cleaned up mmu codeAndrew Waterman1-96/+26
2011-05-31[sim] fault on failed addr translationsAndrew Waterman1-1/+21
2011-05-31[sim] minor sim cleanupAndrew Waterman1-16/+6
2011-05-29[sim,opcodes] improved sim build and run performanceAndrew Waterman1-50/+44
2011-05-28[fesvr,xcc,sim] fixed multicore sim for akarosAndrew Waterman1-14/+23
2011-05-16[sim,pk] cleanups & initial virtual memory supportAndrew Waterman1-38/+46
2011-05-13[sim] initial support for virtual memoryAndrew Waterman1-17/+126
2011-05-06[sim] fixed building sim without cache simulatorsAndrew Waterman1-1/+1
2011-04-30[sim] hacked in a dcache simulatorAndrew Waterman1-1/+33
2011-04-15[sim] added icache simulator (disabled by default)Andrew Waterman1-0/+9
2011-04-12[sim,pk] fixed minor pk bugs and trap codesAndrew Waterman1-3/+5
2011-04-11[xcc,sim,opcodes] more rvc instructions and bug fixesAndrew Waterman1-3/+1
2011-04-09[xcc, sim] added rvc insn c.li; misc fixesAndrew Waterman1-1/+4
2011-04-09[xcc,pk,sim,opcodes] added first RVC instructionAndrew Waterman1-3/+8
2010-10-05[xcc,sim] eliminated vectored trapsAndrew Waterman1-2/+2
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