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path: root/riscv/mmu.h
AgeCommit message (Expand)AuthorFilesLines
2020-07-09Implement hypervisor two-stage MMUAnup Patel1-36/+84
2020-07-08Extend trap classes to pass more informationAnup Patel1-10/+10
2020-06-08Fix priority of misaligned exceptions for store-conditionalAndrew Waterman1-1/+4
2020-03-23commitlog: fix wrong dump when exception occursChih-Min Chao1-1/+1
2020-02-20Disallow access to debug memory region unless in debug modeAndrew Waterman1-0/+3
2020-01-13commitlog: extend load/store record to keep multiple accessChih-Min Chao1-9/+4
2019-12-16extend the commit and memory writes log feature with memory reads (#370)John Ingalls1-6/+21
2019-10-28Implement support for big-endian hostsMarcus Comstedt1-16/+19
2019-10-16Enforce 2^56-bit physical address limitAndrew Waterman1-0/+1
2019-09-18Extends the commit log feature with memory writes. (#324)dave-estes-syzexion1-1/+15
2019-01-28Fix PMP checks for partially-matching accesses (#270)Andrew Waterman1-1/+1
2018-09-25Add PMP supportAndrew Waterman1-3/+6
2018-08-10Fix 2 trigger corner cases. (#229)Tim Newsome1-3/+9
2018-07-10Refactor and fix LR/SC implementation (#217)Andrew Waterman1-0/+24
2018-05-31Put simif_t declaration in its own file. (#209)Andy Wright1-1/+1
2018-04-04Allow querying the mmu configuration chosen during the build. (#191)Prashanth Mundkur1-0/+18
2018-03-06Narrow the interface used by the processors and memory to the top-level simul...Prashanth Mundkur1-2/+2
2018-02-21Don't allow 32-bit instructions to take up multiple slots in I$Andrew Waterman1-1/+2
2017-11-27Rename badaddr to tvalAndrew Waterman1-2/+2
2017-11-27Rename sptbr to satpAndrew Waterman1-10/+10
2017-09-28Implement Q extensionAndrew Waterman1-0/+19
2017-04-30Store both host & target address in soft TLBAndrew Waterman1-20/+29
2017-04-05Add --enable-misaligned option for misaligned ld/st supportAndrew Waterman1-4/+26
2017-03-27Separate page faults from physical memory access exceptionsAndrew Waterman1-0/+3
2017-02-08Encode VM type in sptbr, not mstatusAndrew Waterman1-0/+31
2016-11-13Fix 32-bit host portability bugAndrew Waterman1-1/+1
2016-11-10AMOs should always return store faults, not load faultsAndrew Waterman1-0/+20
2016-09-02Support triggers on TLB misses.Tim Newsome1-0/+3
2016-09-01Theoretically support trigger timing.Tim Newsome1-0/+3
2016-08-22Implement address and data triggers.Tim Newsome1-0/+55
2016-07-06Update to new PTE formatAndrew Waterman1-1/+1
2016-06-22Don't use I$ in debug modeAndrew Waterman1-3/+4
2016-05-23Use fence.i in Debug ROM.Tim Newsome1-1/+0
2016-05-23gdb can attach and read the PC:Tim Newsome1-0/+1
2016-05-23Add debug_module bus device.Tim Newsome1-2/+4
2016-04-29Move much closer to new platform-M memory mapAndrew Waterman1-10/+6
2016-03-02implement PUM functionalityAndrew Waterman1-1/+1
2015-09-24Refactor memory access code; add MMIO supportAndrew Waterman1-36/+38
2015-09-24Use enum instead of two bools to denote memory access typeAndrew Waterman1-19/+21
2015-09-08Improve instruction fetchAndrew Waterman1-15/+15
2015-07-10fix clang compile errorScott Beamer1-0/+1
2015-04-25Fix I$ simulator hit countAndrew Waterman1-4/+5
2015-04-03Support setting ISA/subsets with --isa flagAndrew Waterman1-7/+2
2015-03-30Implement RVC draftAndrew Waterman1-12/+11
2015-03-26New virtual memory implementation (Sv39)Andrew Waterman1-4/+3
2015-03-14Don't set dirty/referenced bits w/o permissionAndrew Waterman1-1/+1
2015-03-12Implement PTE referenced/dirty bitsAndrew Waterman1-2/+2
2015-01-02Require 4-byte instruction alignment until RVC is reimplementedAndrew Waterman1-1/+2
2015-01-02On misaligned fetch, set EPC to target, not branch itselfAndrew Waterman1-1/+3
2015-01-02Reduce dependences on auto-generated codeAndrew Waterman1-3/+4
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