Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2020-05-19 | Rename n_pmp constant to max_pmp | Andrew Waterman | 1 | -2/+2 | |
2020-03-03 | Allow debug accesses from MMUs not bound to processors | Andrew Waterman | 1 | -1/+1 | |
2020-03-03 | Disallow access to debug memory region unless in debug mode | Andrew Waterman | 1 | -3/+28 | |
... as recommended, but not required, by the spec. | |||||
2019-10-29 | Implement support for big-endian hosts | Marcus Comstedt | 1 | -2/+2 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-07-22 | Add debug_mode state bit, rather than overloading dcsr.cause | Andrew Waterman | 1 | -1/+1 | |
In the previous scheme, debug-mode software could exit debug mode by zeroing the dcsr.cause field. While benign, that behavior is out of spec. | |||||
2019-05-14 | Further fix PMP checks for partially-matching accesses (#270) | Andrew Waterman | 1 | -3/+4 | |
ee6fe6501a21ea8d167b6a5048527ba9eb924878 didn't get this right, as it failed to add the offset to the address when checking each 4-byte sector of the access against hte PMPs. | |||||
2019-04-06 | Fix PMP checks for partially-matching accesses (#270) | Andrew Waterman | 1 | -7/+20 | |
PMP checks should unconditionally fail if the PMP matches part of, but not all of, an access. We got this right, but went too far: we checked whether _any_ PMP matches in this manner. In fact, only the first PMP that maches any of the bytes should be checked in this manner. | |||||
2018-09-25 | Add PMP support | Andrew Waterman | 1 | -21/+105 | |
2018-07-10 | Refactor and fix LR/SC implementation (#217) | Andrew Waterman | 1 | -0/+1 | |
- Use physical addresses to avoid homonym ambiguity (closes #215) - Yield reservation on store-conditional (https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612) - Don't yield reservation on exceptions (it's no longer required). | |||||
2018-05-31 | Put simif_t declaration in its own file. (#209) | Andy Wright | 1 | -1/+1 | |
By separating the simif_t declaration from the sim_t declaration, the simif_t declaration no longer depends on fesvr header files. This simplifies compilation of custom sim class implementations that don't depend on fesvr. | |||||
2018-03-21 | Fix the access exception during page-table walks to match the original ↵ | Prashanth Mundkur | 1 | -1/+9 | |
access type, as specified in the manual. (#185) | |||||
2018-03-06 | Narrow the interface used by the processors and memory to the top-level ↵ | Prashanth Mundkur | 1 | -1/+1 | |
simulator/htif. This allows the implementation of an alternative top-level simulator class. | |||||
2017-11-27 | Rename sptbr to satp | Andrew Waterman | 1 | -1/+1 | |
2017-06-07 | Forbid S-mode execution from user memory | Andrew Waterman | 1 | -2/+2 | |
https://github.com/riscv/riscv-isa-manual/commit/285c81746fe664060b62ae0584865dbfa9f42e1a | |||||
2017-05-05 | Trap superpage PTEs when PPN LSBs are set | Andrew Waterman | 1 | -0/+2 | |
2017-04-30 | Store both host & target address in soft TLB | Andrew Waterman | 1 | -16/+17 | |
2017-03-27 | Separate page faults from physical memory access exceptions | Andrew Waterman | 1 | -4/+4 | |
2017-03-20 | PUM -> SUM; expose MXR to S-mode | Andrew Waterman | 1 | -2/+2 | |
2017-02-18 | Make HW setting of PTE A/D bits optional (by configure arg) | Andrew Waterman | 1 | -1/+8 | |
https://github.com/riscv/riscv-isa-manual/issues/14 | |||||
2017-02-08 | Encode VM type in sptbr, not mstatus | Andrew Waterman | 1 | -29/+18 | |
https://github.com/riscv/riscv-isa-manual/issues/4 Also, refactor gdbserver code to not duplicate VM decoding logic. | |||||
2016-09-02 | Support triggers on TLB misses. | Tim Newsome | 1 | -0/+42 | |
2016-08-22 | Implement address and data triggers. | Tim Newsome | 1 | -4/+16 | |
So far I only have testcases for instruction and data address. Not implemented is the mechanism that lets the debugger prevent a user program from using triggers at all. I'll be adding that soonish. The critical path is unchanged, but my experimenting shows the simulation is slowed down about 8% by this code. Reducing the size of trigger_match() (which is never called during my benchmark) fixes that, but making it not be inlined has no effect. I suspect the slowdown comes from cache alignment or something similar, and on a different CPU or after more code changes the speed will come back. | |||||
2016-07-12 | Fix page table walker not respecting valid bit | Andrew Waterman | 1 | -1/+1 | |
2016-07-06 | Update to new PTE format | Andrew Waterman | 1 | -8/+14 | |
2016-05-23 | Turn off debugging. | Tim Newsome | 1 | -9/+0 | |
All the printfs would be pretty annoying if you're actually using this to debug something. Also fixed a small jump bug in halt. | |||||
2016-05-23 | Ignore MPRV in Debug Mode. | Tim Newsome | 1 | -1/+1 | |
2016-05-23 | mprv test now breaks like it's supposed to. | Tim Newsome | 1 | -0/+9 | |
2016-05-23 | Fix off-by-two in general read registers. | Tim Newsome | 1 | -4/+0 | |
Now the exit test passes! | |||||
2016-05-23 | Walk page tables to translate addresses. | Tim Newsome | 1 | -3/+4 | |
2016-05-23 | Remove unused code. | Tim Newsome | 1 | -0/+4 | |
Add some debug printfs, which I'll be wanting for at least a little while. | |||||
2016-05-23 | Have Debug memory kind of working again. | Tim Newsome | 1 | -22/+0 | |
Debug exception -> ROM -> RAM -> ROM, then something goes wrong. | |||||
2016-05-23 | Add debug_module bus device. | Tim Newsome | 1 | -4/+32 | |
This should replace the ROM hack I implemented earlier, but for now both exist together. Back to the point where gdb connects, core jumps to ROM->RAM->ROM. | |||||
2016-05-23 | Can jump to and execute Debug ROM. | Tim Newsome | 1 | -0/+1 | |
Connect with gdb, and the core will jump to Debug ROM and start executing it. Then it crashes when it jumps to 0x400 because Debug RAM isn't implemented (and doesn't live there anyway, for now). | |||||
2016-04-29 | Move much closer to new platform-M memory map | Andrew Waterman | 1 | -15/+18 | |
Reset vector is at 0x1000; below that is reserved for debug Memory is at 0x80000000 | |||||
2016-03-02 | implement PUM functionality | Andrew Waterman | 1 | -5/+10 | |
2016-03-02 | sptbr now a holds a PPN, not an address | Andrew Waterman | 1 | -1/+1 | |
2016-03-02 | WIP on priv spec v1.9 | Andrew Waterman | 1 | -3/+4 | |
2016-02-03 | Actually refill ITLB on ITLB miss | Andrew Waterman | 1 | -1/+3 | |
oops. | |||||
2015-11-12 | Generate device tree for target machine | Andrew Waterman | 1 | -2/+2 | |
2015-10-13 | Fix --dc flag | Andrew Waterman | 1 | -2/+6 | |
Resolves #33. | |||||
2015-09-24 | Refactor memory access code; add MMIO support | Andrew Waterman | 1 | -47/+56 | |
Of course, it doesn't do anything yet. | |||||
2015-09-24 | Use enum instead of two bools to denote memory access type | Andrew Waterman | 1 | -13/+13 | |
2015-05-09 | Upgrade to privileged architecture 1.7 | Andrew Waterman | 1 | -41/+43 | |
2015-04-25 | Fix I$ simulator hit count | Andrew Waterman | 1 | -1/+2 | |
Also, improve performance by allowing the soft-ITLB to refill. | |||||
2015-04-03 | Support setting ISA/subsets with --isa flag | Andrew Waterman | 1 | -8/+15 | |
Default is RV64IMAFDC. Can do things like --isa=RV32 (which implies IMAFDC) --isa=IM (which implies RV64) --isa=RV64IMAFDXhwacha | |||||
2015-03-26 | New virtual memory implementation (Sv39) | Andrew Waterman | 1 | -42/+38 | |
2015-03-14 | Don't set dirty/referenced bits w/o permission | Andrew Waterman | 1 | -14/+15 | |
2015-03-12 | Implement PTE referenced/dirty bits | Andrew Waterman | 1 | -12/+12 | |
2015-03-12 | Update to new privileged spec | Andrew Waterman | 1 | -47/+55 | |
Sorry, everyone. | |||||
2015-01-02 | Reduce dependences on auto-generated code | Andrew Waterman | 1 | -1/+1 | |
In particular, precompiled headers ideally won't depend on any. |