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2020-05-19Rename n_pmp constant to max_pmpAndrew Waterman1-2/+2
2020-03-03Allow debug accesses from MMUs not bound to processorsAndrew Waterman1-1/+1
2020-03-03Disallow access to debug memory region unless in debug modeAndrew Waterman1-3/+28
... as recommended, but not required, by the spec.
2019-10-29Implement support for big-endian hostsMarcus Comstedt1-2/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-07-22Add debug_mode state bit, rather than overloading dcsr.causeAndrew Waterman1-1/+1
In the previous scheme, debug-mode software could exit debug mode by zeroing the dcsr.cause field. While benign, that behavior is out of spec.
2019-05-14Further fix PMP checks for partially-matching accesses (#270)Andrew Waterman1-3/+4
ee6fe6501a21ea8d167b6a5048527ba9eb924878 didn't get this right, as it failed to add the offset to the address when checking each 4-byte sector of the access against hte PMPs.
2019-04-06Fix PMP checks for partially-matching accesses (#270)Andrew Waterman1-7/+20
PMP checks should unconditionally fail if the PMP matches part of, but not all of, an access. We got this right, but went too far: we checked whether _any_ PMP matches in this manner. In fact, only the first PMP that maches any of the bytes should be checked in this manner.
2018-09-25Add PMP supportAndrew Waterman1-21/+105
2018-07-10Refactor and fix LR/SC implementation (#217)Andrew Waterman1-0/+1
- Use physical addresses to avoid homonym ambiguity (closes #215) - Yield reservation on store-conditional (https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612) - Don't yield reservation on exceptions (it's no longer required).
2018-05-31Put simif_t declaration in its own file. (#209)Andy Wright1-1/+1
By separating the simif_t declaration from the sim_t declaration, the simif_t declaration no longer depends on fesvr header files. This simplifies compilation of custom sim class implementations that don't depend on fesvr.
2018-03-21Fix the access exception during page-table walks to match the original ↵Prashanth Mundkur1-1/+9
access type, as specified in the manual. (#185)
2018-03-06Narrow the interface used by the processors and memory to the top-level ↵Prashanth Mundkur1-1/+1
simulator/htif. This allows the implementation of an alternative top-level simulator class.
2017-11-27Rename sptbr to satpAndrew Waterman1-1/+1
2017-06-07Forbid S-mode execution from user memoryAndrew Waterman1-2/+2
https://github.com/riscv/riscv-isa-manual/commit/285c81746fe664060b62ae0584865dbfa9f42e1a
2017-05-05Trap superpage PTEs when PPN LSBs are setAndrew Waterman1-0/+2
2017-04-30Store both host & target address in soft TLBAndrew Waterman1-16/+17
2017-03-27Separate page faults from physical memory access exceptionsAndrew Waterman1-4/+4
2017-03-20PUM -> SUM; expose MXR to S-modeAndrew Waterman1-2/+2
2017-02-18Make HW setting of PTE A/D bits optional (by configure arg)Andrew Waterman1-1/+8
https://github.com/riscv/riscv-isa-manual/issues/14
2017-02-08Encode VM type in sptbr, not mstatusAndrew Waterman1-29/+18
https://github.com/riscv/riscv-isa-manual/issues/4 Also, refactor gdbserver code to not duplicate VM decoding logic.
2016-09-02Support triggers on TLB misses.Tim Newsome1-0/+42
2016-08-22Implement address and data triggers.Tim Newsome1-4/+16
So far I only have testcases for instruction and data address. Not implemented is the mechanism that lets the debugger prevent a user program from using triggers at all. I'll be adding that soonish. The critical path is unchanged, but my experimenting shows the simulation is slowed down about 8% by this code. Reducing the size of trigger_match() (which is never called during my benchmark) fixes that, but making it not be inlined has no effect. I suspect the slowdown comes from cache alignment or something similar, and on a different CPU or after more code changes the speed will come back.
2016-07-12Fix page table walker not respecting valid bitAndrew Waterman1-1/+1
2016-07-06Update to new PTE formatAndrew Waterman1-8/+14
2016-05-23Turn off debugging.Tim Newsome1-9/+0
All the printfs would be pretty annoying if you're actually using this to debug something. Also fixed a small jump bug in halt.
2016-05-23Ignore MPRV in Debug Mode.Tim Newsome1-1/+1
2016-05-23mprv test now breaks like it's supposed to.Tim Newsome1-0/+9
2016-05-23Fix off-by-two in general read registers.Tim Newsome1-4/+0
Now the exit test passes!
2016-05-23Walk page tables to translate addresses.Tim Newsome1-3/+4
2016-05-23Remove unused code.Tim Newsome1-0/+4
Add some debug printfs, which I'll be wanting for at least a little while.
2016-05-23Have Debug memory kind of working again.Tim Newsome1-22/+0
Debug exception -> ROM -> RAM -> ROM, then something goes wrong.
2016-05-23Add debug_module bus device.Tim Newsome1-4/+32
This should replace the ROM hack I implemented earlier, but for now both exist together. Back to the point where gdb connects, core jumps to ROM->RAM->ROM.
2016-05-23Can jump to and execute Debug ROM.Tim Newsome1-0/+1
Connect with gdb, and the core will jump to Debug ROM and start executing it. Then it crashes when it jumps to 0x400 because Debug RAM isn't implemented (and doesn't live there anyway, for now).
2016-04-29Move much closer to new platform-M memory mapAndrew Waterman1-15/+18
Reset vector is at 0x1000; below that is reserved for debug Memory is at 0x80000000
2016-03-02implement PUM functionalityAndrew Waterman1-5/+10
2016-03-02sptbr now a holds a PPN, not an addressAndrew Waterman1-1/+1
2016-03-02WIP on priv spec v1.9Andrew Waterman1-3/+4
2016-02-03Actually refill ITLB on ITLB missAndrew Waterman1-1/+3
oops.
2015-11-12Generate device tree for target machineAndrew Waterman1-2/+2
2015-10-13Fix --dc flagAndrew Waterman1-2/+6
Resolves #33.
2015-09-24Refactor memory access code; add MMIO supportAndrew Waterman1-47/+56
Of course, it doesn't do anything yet.
2015-09-24Use enum instead of two bools to denote memory access typeAndrew Waterman1-13/+13
2015-05-09Upgrade to privileged architecture 1.7Andrew Waterman1-41/+43
2015-04-25Fix I$ simulator hit countAndrew Waterman1-1/+2
Also, improve performance by allowing the soft-ITLB to refill.
2015-04-03Support setting ISA/subsets with --isa flagAndrew Waterman1-8/+15
Default is RV64IMAFDC. Can do things like --isa=RV32 (which implies IMAFDC) --isa=IM (which implies RV64) --isa=RV64IMAFDXhwacha
2015-03-26New virtual memory implementation (Sv39)Andrew Waterman1-42/+38
2015-03-14Don't set dirty/referenced bits w/o permissionAndrew Waterman1-14/+15
2015-03-12Implement PTE referenced/dirty bitsAndrew Waterman1-12/+12
2015-03-12Update to new privileged specAndrew Waterman1-47/+55
Sorry, everyone.
2015-01-02Reduce dependences on auto-generated codeAndrew Waterman1-1/+1
In particular, precompiled headers ideally won't depend on any.
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