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AgeCommit message (Expand)AuthorFilesLines
2020-05-19Rename n_pmp constant to max_pmpAndrew Waterman1-2/+2
2020-03-03Allow debug accesses from MMUs not bound to processorsAndrew Waterman1-1/+1
2020-03-03Disallow access to debug memory region unless in debug modeAndrew Waterman1-3/+28
2019-10-29Implement support for big-endian hostsMarcus Comstedt1-2/+2
2019-07-22Add debug_mode state bit, rather than overloading dcsr.causeAndrew Waterman1-1/+1
2019-05-14Further fix PMP checks for partially-matching accesses (#270)Andrew Waterman1-3/+4
2019-04-06Fix PMP checks for partially-matching accesses (#270)Andrew Waterman1-7/+20
2018-09-25Add PMP supportAndrew Waterman1-21/+105
2018-07-10Refactor and fix LR/SC implementation (#217)Andrew Waterman1-0/+1
2018-05-31Put simif_t declaration in its own file. (#209)Andy Wright1-1/+1
2018-03-21Fix the access exception during page-table walks to match the original access...Prashanth Mundkur1-1/+9
2018-03-06Narrow the interface used by the processors and memory to the top-level simul...Prashanth Mundkur1-1/+1
2017-11-27Rename sptbr to satpAndrew Waterman1-1/+1
2017-06-07Forbid S-mode execution from user memoryAndrew Waterman1-2/+2
2017-05-05Trap superpage PTEs when PPN LSBs are setAndrew Waterman1-0/+2
2017-04-30Store both host & target address in soft TLBAndrew Waterman1-16/+17
2017-03-27Separate page faults from physical memory access exceptionsAndrew Waterman1-4/+4
2017-03-20PUM -> SUM; expose MXR to S-modeAndrew Waterman1-2/+2
2017-02-18Make HW setting of PTE A/D bits optional (by configure arg)Andrew Waterman1-1/+8
2017-02-08Encode VM type in sptbr, not mstatusAndrew Waterman1-29/+18
2016-09-02Support triggers on TLB misses.Tim Newsome1-0/+42
2016-08-22Implement address and data triggers.Tim Newsome1-4/+16
2016-07-12Fix page table walker not respecting valid bitAndrew Waterman1-1/+1
2016-07-06Update to new PTE formatAndrew Waterman1-8/+14
2016-05-23Turn off debugging.Tim Newsome1-9/+0
2016-05-23Ignore MPRV in Debug Mode.Tim Newsome1-1/+1
2016-05-23mprv test now breaks like it's supposed to.Tim Newsome1-0/+9
2016-05-23Fix off-by-two in general read registers.Tim Newsome1-4/+0
2016-05-23Walk page tables to translate addresses.Tim Newsome1-3/+4
2016-05-23Remove unused code.Tim Newsome1-0/+4
2016-05-23Have Debug memory kind of working again.Tim Newsome1-22/+0
2016-05-23Add debug_module bus device.Tim Newsome1-4/+32
2016-05-23Can jump to and execute Debug ROM.Tim Newsome1-0/+1
2016-04-29Move much closer to new platform-M memory mapAndrew Waterman1-15/+18
2016-03-02implement PUM functionalityAndrew Waterman1-5/+10
2016-03-02sptbr now a holds a PPN, not an addressAndrew Waterman1-1/+1
2016-03-02WIP on priv spec v1.9Andrew Waterman1-3/+4
2016-02-03Actually refill ITLB on ITLB missAndrew Waterman1-1/+3
2015-11-12Generate device tree for target machineAndrew Waterman1-2/+2
2015-10-13Fix --dc flagAndrew Waterman1-2/+6
2015-09-24Refactor memory access code; add MMIO supportAndrew Waterman1-47/+56
2015-09-24Use enum instead of two bools to denote memory access typeAndrew Waterman1-13/+13
2015-05-09Upgrade to privileged architecture 1.7Andrew Waterman1-41/+43
2015-04-25Fix I$ simulator hit countAndrew Waterman1-1/+2
2015-04-03Support setting ISA/subsets with --isa flagAndrew Waterman1-8/+15
2015-03-26New virtual memory implementation (Sv39)Andrew Waterman1-42/+38
2015-03-14Don't set dirty/referenced bits w/o permissionAndrew Waterman1-14/+15
2015-03-12Implement PTE referenced/dirty bitsAndrew Waterman1-12/+12
2015-03-12Update to new privileged specAndrew Waterman1-47/+55
2015-01-02Reduce dependences on auto-generated codeAndrew Waterman1-1/+1
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