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2022-10-14In triggers, use optional<data> instead of {has_data, data}Andrew Waterman1-7/+7
2022-10-13Remove unused field matched_t::dataAndrew Waterman1-2/+2
2022-10-06Don't use reexecution as the means to implement trigger-afterAndrew Waterman1-1/+4
The scheme was based on the notion that memory accesses are idempotent up until the point the trigger would've been hit, which isn't true in the case of side-effecting loads and data-value triggers. Instead, check the trigger on the next instruction fetch. To keep the perf overhead minimal, perform this check on the I$ refill path, and ensure that path is taken by flushing the I$.
2022-10-06Fix endianness bug in fetch triggersAndrew Waterman1-2/+1
Instruction fetch is always little-endian.
2022-10-06DRY in checking triggersAndrew Waterman1-26/+27
2022-10-06Move uncommon-case fetch functionality into fetch_slow_pathAndrew Waterman1-8/+24
2022-10-06Move all uncommon-case store functionality into store_slow_pathAndrew Waterman1-8/+35
As a side effect, misaligned stores now behave the same as aligned stores with respect to triggers: only the first byte is checked.
2022-10-06Move all uncommon-case load functionality into load_slow_pathAndrew Waterman1-5/+32
As a side effect, misaligned loads now behave the same as aligned loads with respect to triggers: only the first byte is checked.
2022-10-05Remove unused variable to fix buildAndrew Waterman1-1/+0
2022-10-05Merge pull request #1105 from YenHaoChen/pr-trigger-priorityAndrew Waterman1-8/+17
Fix trigger priority
2022-10-04Suppress most unused variable warningsAndrew Waterman1-1/+1
2022-09-30Check trigger only with actually_storeYenHaoChen1-5/+7
The data value of the function store_slow_path() is meaningful only when the actually_store=true. Otherwise, the data value is a hollow value of 0, which may result in unintended trigger matching.
2022-09-30Fix priority of mcontrol trigger store address/data beforeYenHaoChen1-2/+2
The spec defines that the mcontrol store address/data has a higher priority over page fault and address misalignment (Debug spec, Table 5.2). Thus, the trigger checking should be before the translation and alignment checking. The previous implementation checks the trigger after the translation and alignment, resulting in incorrect priority. For instance, when page fault and trigger occur on the same instruction, the previous implementation will choose to raise the page fault, which contradicts the priority requirement. This commit moves the trigger checking before the misaligned checking and translation. The trigger will fire on the instruction instead of the page fault in the above case.
2022-09-30Fix priority of mcontrol trigger load address beforeYenHaoChen1-0/+7
The spec defines the mcontrol load address has a higher priority over page fault and address misaligned (Debug spec, Table 5.2). Thus, the trigger checking should be before the translation and alignment checking. The previous implementation checks the trigger after the translation and alignment, resulting in incorrect priority. For instance, when page fault and trigger occur on the same instruction, the previous implementation will choose to raise the page fault, which contradicts the priority requirement. This commit adds an address-only trigger checking before the misaligned checking and translation. The trigger will fire on the instruction instead of the page fault in the above case.
2022-09-30Add has_data argument to trigger checking functionsYenHaoChen1-2/+2
The mcontrol trigger can select either address or data for checking. The The selection decides the priority of the trigger. For instance, the address trigger has a higher priority over the page fault, and the page fault has a higher priority over the data trigger. The previous implementation only has the checking functions for data trigger, which results in incorrect priority of address trigger. This commit adds a has_data argument to indicate address trigger and the priority of the trigger.
2022-05-11Check for reserved PBMT values during tablewalks and fault if foundRyan Buchner1-0/+4
See #990.
2022-05-11Switch from checking for SVPBMT extension to checking *ENVCFG values during ↵Ryan Buchner1-2/+4
tablewalks Fix issue #990.
2022-05-04Update mmu_t::pmp_ok() for ePMP in case matching region is not foundsoberl@nvidia.com1-1/+5
2022-04-13Adjust indentation in store_slow_path and store_funcRyan Buchner1-9/+9
Didn't want to make change in previous commit to isolate the change.
2022-04-13Skip storing in store_func if actually_store is false, add a fake store at ↵Ryan Buchner1-0/+2
start of AMO. This includes skipping store in store_slow_path. Is okay to skip the mmio_store part too, since the access_fault for mmio_failure will be caught on the actual store. The ordering for the mmio_access fault is irrelevant since it will occur after the TW faults, and load faults are converted to store faults. Will catch any faults from the access but won't perform a store. Since store permissions can only be granted if read permissions exist, any store faults will occur before or at the same time as a load fault. Thus this store permissions check is sufficient for properly catching the faults in an Amo access TW.
2022-04-12Add actually_store tag to store_func and store_slow_pathRyan Buchner1-1/+1
Will be used to check store attributes without actually performing the store. Needed to AMO bug fix.
2022-03-30trigger_operation_t -> triggers::operation_tTim Newsome1-2/+2
2021-12-05page fault when PTE_N bit set and not EXT_SVNAPOT (#875)John Ingalls1-0/+4
2021-12-04page fault when PTE_PBMT bits set and not EXT_SVPBMT (#874)John Ingalls1-0/+4
2021-11-29Reindent s2xlate()Scott Johnson1-49/+49
2021-11-29Raise guest page fault if GPA is out of rangeScott Johnson1-0/+5
Based on this statement from priv spec 5.5.1 (regarding Sv39x4): "Address bits 63:41 must all be zeros, or else a guest-page-fault exception occurs."
2021-09-25Convert hgatp to csr_tScott Johnson1-1/+1
2021-09-08Use virtualized_csr_t for satp and vsatpScott Johnson1-1/+1
This was much more complicated than the others because of the mstatus.TVM and hstatus.VTVM bits, and because of the special WARL-ness of satp that doesn't apply to vsatp. It appears (based on reading the code) that the commitlog for these two was problematic. CSRW to satp when V=1 was reporting a write to satp instead of vsatp which was actually written. Also a CSRW to vsatp looks like it was not being logged at all. Both problems should be fixed now.
2021-09-08Convert hstatus to csr_t familyScott Johnson1-1/+1
2021-09-08Add get_const_xlen() as a way to document assumptions of unchanging xlenScott Johnson1-2/+2
Spike does not support dynamic xlen today, but if it should in the future, this will help identify all the code that needs to be updated.
2021-09-08Simplify calculation of mxrScott Johnson1-3/+1
2021-09-08Convert sstatus to virtualized_csr_tScott Johnson1-5/+4
Step 5 of plan in csrs.h. This changes the commitlog to properly report when the architectural `vsstatus` register is written, e.g. by `csrw sstatus` in VS-mode.
2021-09-08Convert mstatus into csr_t familyScott Johnson1-4/+4
Step 3 of plan described in csrs.h.
2021-09-08Convert mmu_t::walk to use sstatusScott Johnson1-4/+4
Part of step 2 of plan described in csrs.h.
2021-09-08Convert s2xlate() to use sstatusScott Johnson1-2/+2
Part of step 2 of plan described in csrs.h.
2021-09-08Convert vsstatus to csr_t familyScott Johnson1-3/+3
Makes a mess out of the tracing though, because of how every toggle of the VBit swaps mstatus and vsstatus.
2021-09-08Remove unnecessary check of procScott Johnson1-1/+1
We've already checked just a few lines up that proc is defined.
2021-09-08Move permissions check into pmpaddr_csr_tScott Johnson1-6/+1
This was the last place outside of the csr_t hierarchy that pmpcfg was being accessed.
2021-09-08Make pmp_ok return type boolScott Johnson1-1/+1
Since that's what it was returning anyway.
2021-09-08Move homogeneity detection into pmpaddr_csr_tScott Johnson1-22/+3
2021-09-08Remove unnecessary check for PMP_OFFScott Johnson1-23/+19
Since match4() checks this now.
2021-09-08Add new method match4()Scott Johnson1-6/+1
To simplify calling code.
2021-09-08Add tor_base_paddr() method to pmpaddrScott Johnson1-6/+2
This will enable further restructuring of these loops in mmu.cc in the next commits.
2021-09-08Add napot_mask() function to simplify callersScott Johnson1-9/+2
2021-09-08Add tor_paddr() method to simplify callersScott Johnson1-2/+2
2021-09-08Convert pmpaddr* to csr_t familyScott Johnson1-4/+4
2021-09-02Use correct CSR for SUM/MXR for VS-mode load/stores (#792)Scott Johnson1-3/+6
See discussion at https://github.com/riscv/riscv-isa-sim/commit/9cfc3e7fef7b29f6b53879d7c91c35459d9b493d#r55593451
2021-08-06Non-leaf PTEs should not have N or PBMT bits set (#764)Daniel Lustig1-2/+2
2021-07-22Non-leaf PTEs with D/A/U==1 are reservedAndrew Waterman1-0/+2
Continuation of 80be4e21c3af7fe2966788ce538d3e3c3b0d60e3
2021-07-22Merge branch 'nonleaf_dau' of https://github.com/daniellustig/riscv-isa-sim ↵Andrew Waterman1-0/+2
into daniellustig-nonleaf_dau
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