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AgeCommit message (Expand)AuthorFilesLines
2021-07-22Non-leaf PTEs with D/A/U==1 are reservedDan Lustig1-0/+2
2021-07-21Fix hypervisor MXR and SUMAndrew Waterman1-8/+10
2021-07-21Fix HLVX permissions checkAndrew Waterman1-15/+13
2021-07-21Simplify (and possibly fix) handling of HLV/HSV TLB accessesAndrew Waterman1-2/+2
2021-07-21HLV/HSV instructions should respect SPVP even in debug modeAndrew Waterman1-1/+1
2021-07-20Priv virtual memory updates (#750)Daniel Lustig1-4/+8
2021-07-16Fix MPRV-related bugAndrew Waterman1-1/+5
2021-03-05Don't make MPRV load/store virtual if MPV=1, MPP=3 (#666)jameshippisley1-1/+1
2021-02-08Zsn has been renamed Svnapot (#641)Daniel Lustig1-1/+1
2020-12-18Check and use proc variable in MMU emulationAnup Patel1-3/+3
2020-12-07Oops...napot_bits should use ctz, not clz (#614)Daniel Lustig1-2/+2
2020-11-27Fix hstatus.GVA and mstatus.GVA updationAnup Patel1-15/+15
2020-11-18Don't include PTE.N bit as part of the PPNAndrew Waterman1-2/+2
2020-11-18Invalid NAPOT settings cause page faults, not access exceptionsAndrew Waterman1-2/+2
2020-11-18Add Zsn extensionAndrew Waterman1-3/+18
2020-11-07Tag target endian values to help guide conversion codeMarcus Comstedt1-4/+4
2020-11-07Implement support for big-endian targetsMarcus Comstedt1-4/+7
2020-10-24Fix trap generation in s2xlate()Anup Patel1-7/+7
2020-07-09Implement hypervisor two-stage MMUAnup Patel1-15/+95
2020-07-08Extend trap classes to pass more informationAnup Patel1-9/+9
2020-05-10Implement coarse-grain PMP matching logicAndrew Waterman1-6/+6
2020-05-10Disable PMP checks when configuration includes zero PMP registersAndrew Waterman1-1/+1
2020-05-09Rename n_pmp constant to max_pmpAndrew Waterman1-2/+2
2020-02-21Allow debug accesses from MMUs not bound to processorsAndrew Waterman1-1/+1
2020-02-20Disallow access to debug memory region unless in debug modeAndrew Waterman1-3/+28
2019-10-28Implement support for big-endian hostsMarcus Comstedt1-2/+2
2019-07-12Add debug_mode state bit, rather than overloading dcsr.causeAndrew Waterman1-1/+1
2019-02-28Further fix PMP checks for partially-matching accesses (#270)Andrew Waterman1-3/+4
2019-01-28Fix PMP checks for partially-matching accesses (#270)Andrew Waterman1-7/+20
2018-09-25Add PMP supportAndrew Waterman1-21/+105
2018-07-10Refactor and fix LR/SC implementation (#217)Andrew Waterman1-0/+1
2018-05-31Put simif_t declaration in its own file. (#209)Andy Wright1-1/+1
2018-03-21Fix the access exception during page-table walks to match the original access...Prashanth Mundkur1-1/+9
2018-03-06Narrow the interface used by the processors and memory to the top-level simul...Prashanth Mundkur1-1/+1
2017-11-27Rename sptbr to satpAndrew Waterman1-1/+1
2017-06-07Forbid S-mode execution from user memoryAndrew Waterman1-2/+2
2017-05-05Trap superpage PTEs when PPN LSBs are setAndrew Waterman1-0/+2
2017-04-30Store both host & target address in soft TLBAndrew Waterman1-16/+17
2017-03-27Separate page faults from physical memory access exceptionsAndrew Waterman1-4/+4
2017-03-20PUM -> SUM; expose MXR to S-modeAndrew Waterman1-2/+2
2017-02-18Make HW setting of PTE A/D bits optional (by configure arg)Andrew Waterman1-1/+8
2017-02-08Encode VM type in sptbr, not mstatusAndrew Waterman1-29/+18
2016-09-02Support triggers on TLB misses.Tim Newsome1-0/+42
2016-08-22Implement address and data triggers.Tim Newsome1-4/+16
2016-07-12Fix page table walker not respecting valid bitAndrew Waterman1-1/+1
2016-07-06Update to new PTE formatAndrew Waterman1-8/+14
2016-05-23Turn off debugging.Tim Newsome1-9/+0
2016-05-23Ignore MPRV in Debug Mode.Tim Newsome1-1/+1
2016-05-23mprv test now breaks like it's supposed to.Tim Newsome1-0/+9
2016-05-23Fix off-by-two in general read registers.Tim Newsome1-4/+0
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