index
:
rocket-tools/riscv-gnu-toolchain/spike.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
riscv
/
mmu.cc
Age
Commit message (
Expand
)
Author
Files
Lines
2016-02-03
Actually refill ITLB on ITLB miss
Andrew Waterman
1
-1
/
+3
2015-11-12
Generate device tree for target machine
Andrew Waterman
1
-2
/
+2
2015-10-13
Fix --dc flag
Andrew Waterman
1
-2
/
+6
2015-09-24
Refactor memory access code; add MMIO support
Andrew Waterman
1
-47
/
+56
2015-09-24
Use enum instead of two bools to denote memory access type
Andrew Waterman
1
-13
/
+13
2015-05-09
Upgrade to privileged architecture 1.7
Andrew Waterman
1
-41
/
+43
2015-04-25
Fix I$ simulator hit count
Andrew Waterman
1
-1
/
+2
2015-04-03
Support setting ISA/subsets with --isa flag
Andrew Waterman
1
-8
/
+15
2015-03-26
New virtual memory implementation (Sv39)
Andrew Waterman
1
-42
/
+38
2015-03-14
Don't set dirty/referenced bits w/o permission
Andrew Waterman
1
-14
/
+15
2015-03-12
Implement PTE referenced/dirty bits
Andrew Waterman
1
-12
/
+12
2015-03-12
Update to new privileged spec
Andrew Waterman
1
-47
/
+55
2015-01-02
Reduce dependences on auto-generated code
Andrew Waterman
1
-1
/
+1
2014-12-04
Set badvaddr on instruction page faults
Andrew Waterman
1
-2
/
+1
2014-01-13
Improve performance for branchy code
Andrew Waterman
1
-2
/
+2
2013-12-17
Speed things up quite a bit
Andrew Waterman
1
-4
/
+5
2013-08-11
Instructions are no longer member functions
Andrew Waterman
1
-9
/
+8
2013-07-26
New supervisor mode
Andrew Waterman
1
-13
/
+13
2013-07-26
Generate instruction decoder dynamically
Andrew Waterman
1
-10
/
+4
2013-03-29
add load-reserved/store-conditional instructions
Andrew Waterman
1
-2
/
+9
2013-03-25
add BSD license
Andrew Waterman
1
-0
/
+2
2013-03-25
truncate effective addresses in rv32
Andrew Waterman
1
-3
/
+3
2013-02-15
don't store host pointers in soft TLB
Andrew Waterman
1
-3
/
+3
2013-02-13
clean up fetch-execute loop a bit
Andrew Waterman
1
-6
/
+6
2013-02-13
add I$/D$/L2$ simulators
Andrew Waterman
1
-6
/
+21
2012-03-24
new supervisor mode
Andrew Waterman
1
-1
/
+1
2012-01-30
don't set badvaddr for instruction access faults
Andrew Waterman
1
-3
/
+4
2012-01-24
check that virtual addresses are sign-extended
Andrew Waterman
1
-1
/
+5
2011-11-01
Fixed tight coupling of host and target page size
Andrew Waterman
1
-1
/
+1
2011-06-19
temporary undoing of renaming
Andrew Waterman
1
-0
/
+104
2011-06-12
[sim] renamed to riscv-isa-run
Andrew Waterman
1
-104
/
+0
2011-06-11
[xcc] tlb now stores host addresses
Andrew Waterman
1
-3
/
+3
2011-06-11
[xcc] cleaned up mmu code
Andrew Waterman
1
-2
/
+94
2011-05-16
[sim,pk] cleanups & initial virtual memory support
Andrew Waterman
1
-0
/
+12