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AgeCommit message (Expand)AuthorFilesLines
2015-05-09Upgrade to privileged architecture 1.7Andrew Waterman1-41/+43
2015-04-25Fix I$ simulator hit countAndrew Waterman1-1/+2
2015-04-03Support setting ISA/subsets with --isa flagAndrew Waterman1-8/+15
2015-03-26New virtual memory implementation (Sv39)Andrew Waterman1-42/+38
2015-03-14Don't set dirty/referenced bits w/o permissionAndrew Waterman1-14/+15
2015-03-12Implement PTE referenced/dirty bitsAndrew Waterman1-12/+12
2015-03-12Update to new privileged specAndrew Waterman1-47/+55
2015-01-02Reduce dependences on auto-generated codeAndrew Waterman1-1/+1
2014-12-04Set badvaddr on instruction page faultsAndrew Waterman1-2/+1
2014-01-13Improve performance for branchy codeAndrew Waterman1-2/+2
2013-12-17Speed things up quite a bitAndrew Waterman1-4/+5
2013-08-11Instructions are no longer member functionsAndrew Waterman1-9/+8
2013-07-26New supervisor modeAndrew Waterman1-13/+13
2013-07-26Generate instruction decoder dynamicallyAndrew Waterman1-10/+4
2013-03-29add load-reserved/store-conditional instructionsAndrew Waterman1-2/+9
2013-03-25add BSD licenseAndrew Waterman1-0/+2
2013-03-25truncate effective addresses in rv32Andrew Waterman1-3/+3
2013-02-15don't store host pointers in soft TLBAndrew Waterman1-3/+3
2013-02-13clean up fetch-execute loop a bitAndrew Waterman1-6/+6
2013-02-13add I$/D$/L2$ simulatorsAndrew Waterman1-6/+21
2012-03-24new supervisor modeAndrew Waterman1-1/+1
2012-01-30don't set badvaddr for instruction access faultsAndrew Waterman1-3/+4
2012-01-24check that virtual addresses are sign-extendedAndrew Waterman1-1/+5
2011-11-01Fixed tight coupling of host and target page sizeAndrew Waterman1-1/+1
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+104
2011-06-12[sim] renamed to riscv-isa-runAndrew Waterman1-104/+0
2011-06-11[xcc] tlb now stores host addressesAndrew Waterman1-3/+3
2011-06-11[xcc] cleaned up mmu codeAndrew Waterman1-2/+94
2011-05-16[sim,pk] cleanups & initial virtual memory supportAndrew Waterman1-0/+12
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