rocket-tools/riscv-gnu-toolchain/spike.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-04-27	Implement JTAG BYPASS register. (#697)	Tim Newsome	1	-11/+14
2020-01-13	Make minimum RTI behavior more realistic. (#375)	Tim Newsome	1	-32/+35
2019-07-11	Fix some 32-bit safety issues	Andrew Waterman	1	-2/+2
2018-12-13	Add --dmi-rti and --abstract-rti to test OpenOCD.	Tim Newsome	1	-28/+42
2018-02-27	Add debug module authentication.	Tim Newsome	1	-3/+7
2017-06-08	Reset to "success" instead of "error."dtm_reset_error	Tim Newsome	1	-1/+1
2017-03-21	spec bump	Palmer Dabbelt	1	-1/+1
2017-02-21	Improve debug performance.	Tim Newsome	1	-8/+6
2017-02-15	Implement autoexec. DMI op 2 is just write now.	Tim Newsome	1	-5/+4
2017-02-13	dbus -> dmi	Tim Newsome	1	-23/+23
2017-02-13	Abstract register read mostly working.	Tim Newsome	1	-1/+1
2017-02-12	Fix stack overflow and support --rbb-port=0	Tim Newsome	1	-0/+1
2017-02-08	Serve up a correct dmcontrol register.	Tim Newsome	1	-7/+22
2017-02-07	OpenOCD does a dmi read and gets dummy value back.	Tim Newsome	1	-7/+93
2017-02-06	Refactor remote bitbang code.	Tim Newsome	1	-0/+81