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path: root/riscv/isa_parser.h
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2022-09-20Merge pull request #1036 from plctlab/plct-sscofpmf-devAndrew Waterman1-0/+1
add support for sscofpmf extension v0.5.2
2022-08-10Add space between if/while/switch and '('Weiwei Li1-1/+1
Add space between ')' and '{'
2022-08-09add support for sscofpmf extension v0.5.2Weiwei Li1-0/+1
since spike doesn't truly support counting of hardware performance events, only csr related read/write functions is supported currently
2022-08-03Add Sstc support. (#1057)i2h21-0/+1
2022-07-13add isa string parser for smepmpYenHaoChen1-0/+1
2022-07-07add isa string parser for smstateenWeiwei Li1-0/+1
2022-04-06mmu: support asid/vmid (#928)Chih-Min Chao1-0/+2
The change makes [v]satp.asid and hgatp.vmid writtable and supports maximum length for rv32 and rv64. Software could write and read the satp.asid to get the valid length or check if the core supports asid/vmid or not. However, there is no official way to describe this hardware capability (device tree or something else). Two implementation flags are also added for future use and enabled by default. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2022-03-30Implement Sv57 and Sv57x4 translation modesAndrew Waterman1-0/+1
2022-03-29Split isa_parser_t out of processor.* and into its own file (#955)Rupert Swarbrick1-0/+87
The main motivation for this is that we want to move the ISA parsing logic to run before we even construct a simulator. That's probably a bit nicer if we don't depend on the processor header. It also means that we can stop depending on processor.h in disasm.cc or spike_log_parser.cc (both through disasm.h), which feels a bit cleaner: making sense of an instruction trace shouldn't really require knowledge of the internal state of a processor.