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2020-03-12rvv: fix vfmv.f.s and vfmv.s.fChih-Min Chao2-22/+21
2020-03-11commitlog: fix missing dump for some instructionsChih-Min Chao7-25/+28
2020-03-11rvv: respect vstart and vl for vfmv.s.fChih-Min Chao1-19/+22
2020-03-05rvv: avoid redundant std::string comparisonZhen Wei2-13/+24
2020-03-05rvv: import parallel vf(w)redsum hardware impl.Zhen Wei4-14/+47
2020-03-03rvv: handle middle value of vslidedown.vxChih-Min Chao1-1/+1
2020-03-04rvv: remove the option of vector misaligned accessZhen Wei6-16/+16
2020-02-20Revert "rvv modify the vfredsum.vs behavior with e27 xlen=32"Max Lin1-54/+8
2020-02-20rvv modify the vfredsum.vs behavior with e27 xlen=32Max Lin1-8/+54
2020-02-19rvv: also relax vmerge_vim/vvm when lmul = 1Chih-Min Chao2-2/+0
2020-02-19rvv: also relax lmul in vfwredumChih-Min Chao2-2/+0
2020-02-19Vector stores don't care if rd overlaps v0 (#400)Andrew Waterman4-4/+4
2020-02-19v[f]merge: allow v0 overlap if LMUL = 1Andrew Waterman2-2/+0
2020-02-17rvv: use pre-definied v_simm5() macroChih-Min Chao3-6/+3
2020-02-14rvv: make variable name match its meaningChih-Min Chao5-5/+5
2020-02-14rvv: fix vmsleu/vmsgtu/vsaddu.vi operand signed extensionChih-Min Chao3-3/+6
2020-02-13rvv: reset vstart to 0 when vmv.s.x and vmv.x.s and also check the vstart < v...Dave.Wen2-1/+5
2020-02-12rvv: vms[bio]f.m need to start from 0Chih-Min Chao3-6/+3
2020-02-12Fix incorrect commentsAndrew Waterman2-2/+2
2020-02-12commitlog: rvv: add commitlog support to misc instrutionsChih-Min Chao7-17/+16
2020-02-12commitlog: rvv: add commitlog support to integer instructionsChih-Min Chao1-4/+4
2020-02-12commitlog: rvv: add commitlog support to float instrunctionsChih-Min Chao14-20/+19
2020-02-12rvv: vsbc/vmsbc behavior of the sub order. VI-1849/VI-1761Max Lin4-4/+4
2020-01-15modify vnclipu from u64 to u128Max Lin1-1/+1
2020-01-15modify vssrl_viMax Lin1-1/+1
2020-01-13rvv: vfncvt and vfwcvt need to check the widening supportChih-Min Chao11-0/+33
2020-01-06rvv : vmv[1248]r.vChih-Min Chao6-1/+20
2019-12-19Require VM enabled for SFENCE.VMA and S-mode for mstatus.SUM (#367)Udit Khanna1-0/+1
2019-12-19rvv: fix the exception behavior for fault-first loadAndrew Waterman1-53/+11
2019-12-12rvv: fix vfwcvt/vfncvt for f32 -> f64 and f64 -> f32Chih-Min Chao11-11/+17
2019-12-12rvv: refinve vfmv to support float64Chih-Min Chao4-29/+62
2019-12-12rvv: add vfredxxx.vs and vfwred[o]sum.vs float64 supportChih-Min Chao6-0/+20
2019-12-12rvv: add vmfxxx.v[vf] float64 supportChih-Min Chao10-20/+60
2019-12-12rvv: add vfxxx.vf float64 supportChih-Min Chao22-1/+69
2019-12-12rvv: add vfxxx.vv float64 suuportChih-Min Chao21-0/+63
2019-12-02rvv: fix commentChih-Min Chao1-1/+1
2019-11-28rvv: fix vl1r checking ruleChih-Min Chao2-0/+2
2019-11-27rvv: add whole register load/store, vl1r.v/vs1r.vChih-Min Chao2-0/+18
2019-11-27rvv: make vlx/vsx match 0.8 specChih-Min Chao11-30/+17
2019-11-27rvv: change vmerge/vslideup register checking ruleChih-Min Chao7-3/+7
2019-11-27rvv: change vsetvl[i] to match 0.8 specChih-Min Chao2-2/+2
2019-11-27rvv: remove unsupported widen sewChih-Min Chao1-1/+1
2019-11-27rvv: fix vmadc/vmsbcChih-Min Chao5-5/+5
2019-11-27rvv: fix vadc/vsbcChih-Min Chao5-15/+10
2019-11-27rvv: add unsigned averageChih-Min Chao4-0/+8
2019-11-27rvv: replace vn suffic by 'w'Chih-Min Chao12-0/+0
2019-11-27rvv: fix floating sign inject operand orderChih-Min Chao6-6/+6
2019-11-27rvv: rename vfncvt suffix and add rod rouding typeChih-Min Chao6-3/+10
2019-11-27rvv: add vqm* 'Quad-Widening Integer Multiply-Add'Chih-Min Chao14-14/+35
2019-11-18rvv: remove rest of vaadd_viChih-Min Chao1-10/+0
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