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rocket-tools/riscv-gnu-toolchain/spike.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
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Files
Lines
2020-03-12
rvv: fix vfmv.f.s and vfmv.s.f
Chih-Min Chao
2
-22
/
+21
2020-03-11
commitlog: fix missing dump for some instructions
Chih-Min Chao
7
-25
/
+28
2020-03-11
rvv: respect vstart and vl for vfmv.s.f
Chih-Min Chao
1
-19
/
+22
2020-03-05
rvv: avoid redundant std::string comparison
Zhen Wei
2
-13
/
+24
2020-03-05
rvv: import parallel vf(w)redsum hardware impl.
Zhen Wei
4
-14
/
+47
2020-03-03
rvv: handle middle value of vslidedown.vx
Chih-Min Chao
1
-1
/
+1
2020-03-04
rvv: remove the option of vector misaligned access
Zhen Wei
6
-16
/
+16
2020-02-20
Revert "rvv modify the vfredsum.vs behavior with e27 xlen=32"
Max Lin
1
-54
/
+8
2020-02-20
rvv modify the vfredsum.vs behavior with e27 xlen=32
Max Lin
1
-8
/
+54
2020-02-19
rvv: also relax vmerge_vim/vvm when lmul = 1
Chih-Min Chao
2
-2
/
+0
2020-02-19
rvv: also relax lmul in vfwredum
Chih-Min Chao
2
-2
/
+0
2020-02-19
Vector stores don't care if rd overlaps v0 (#400)
Andrew Waterman
4
-4
/
+4
2020-02-19
v[f]merge: allow v0 overlap if LMUL = 1
Andrew Waterman
2
-2
/
+0
2020-02-17
rvv: use pre-definied v_simm5() macro
Chih-Min Chao
3
-6
/
+3
2020-02-14
rvv: make variable name match its meaning
Chih-Min Chao
5
-5
/
+5
2020-02-14
rvv: fix vmsleu/vmsgtu/vsaddu.vi operand signed extension
Chih-Min Chao
3
-3
/
+6
2020-02-13
rvv: reset vstart to 0 when vmv.s.x and vmv.x.s and also check the vstart < v...
Dave.Wen
2
-1
/
+5
2020-02-12
rvv: vms[bio]f.m need to start from 0
Chih-Min Chao
3
-6
/
+3
2020-02-12
Fix incorrect comments
Andrew Waterman
2
-2
/
+2
2020-02-12
commitlog: rvv: add commitlog support to misc instrutions
Chih-Min Chao
7
-17
/
+16
2020-02-12
commitlog: rvv: add commitlog support to integer instructions
Chih-Min Chao
1
-4
/
+4
2020-02-12
commitlog: rvv: add commitlog support to float instrunctions
Chih-Min Chao
14
-20
/
+19
2020-02-12
rvv: vsbc/vmsbc behavior of the sub order. VI-1849/VI-1761
Max Lin
4
-4
/
+4
2020-01-15
modify vnclipu from u64 to u128
Max Lin
1
-1
/
+1
2020-01-15
modify vssrl_vi
Max Lin
1
-1
/
+1
2020-01-13
rvv: vfncvt and vfwcvt need to check the widening support
Chih-Min Chao
11
-0
/
+33
2020-01-06
rvv : vmv[1248]r.v
Chih-Min Chao
6
-1
/
+20
2019-12-19
Require VM enabled for SFENCE.VMA and S-mode for mstatus.SUM (#367)
Udit Khanna
1
-0
/
+1
2019-12-19
rvv: fix the exception behavior for fault-first load
Andrew Waterman
1
-53
/
+11
2019-12-12
rvv: fix vfwcvt/vfncvt for f32 -> f64 and f64 -> f32
Chih-Min Chao
11
-11
/
+17
2019-12-12
rvv: refinve vfmv to support float64
Chih-Min Chao
4
-29
/
+62
2019-12-12
rvv: add vfredxxx.vs and vfwred[o]sum.vs float64 support
Chih-Min Chao
6
-0
/
+20
2019-12-12
rvv: add vmfxxx.v[vf] float64 support
Chih-Min Chao
10
-20
/
+60
2019-12-12
rvv: add vfxxx.vf float64 support
Chih-Min Chao
22
-1
/
+69
2019-12-12
rvv: add vfxxx.vv float64 suuport
Chih-Min Chao
21
-0
/
+63
2019-12-02
rvv: fix comment
Chih-Min Chao
1
-1
/
+1
2019-11-28
rvv: fix vl1r checking rule
Chih-Min Chao
2
-0
/
+2
2019-11-27
rvv: add whole register load/store, vl1r.v/vs1r.v
Chih-Min Chao
2
-0
/
+18
2019-11-27
rvv: make vlx/vsx match 0.8 spec
Chih-Min Chao
11
-30
/
+17
2019-11-27
rvv: change vmerge/vslideup register checking rule
Chih-Min Chao
7
-3
/
+7
2019-11-27
rvv: change vsetvl[i] to match 0.8 spec
Chih-Min Chao
2
-2
/
+2
2019-11-27
rvv: remove unsupported widen sew
Chih-Min Chao
1
-1
/
+1
2019-11-27
rvv: fix vmadc/vmsbc
Chih-Min Chao
5
-5
/
+5
2019-11-27
rvv: fix vadc/vsbc
Chih-Min Chao
5
-15
/
+10
2019-11-27
rvv: add unsigned average
Chih-Min Chao
4
-0
/
+8
2019-11-27
rvv: replace vn suffic by 'w'
Chih-Min Chao
12
-0
/
+0
2019-11-27
rvv: fix floating sign inject operand order
Chih-Min Chao
6
-6
/
+6
2019-11-27
rvv: rename vfncvt suffix and add rod rouding type
Chih-Min Chao
6
-3
/
+10
2019-11-27
rvv: add vqm* 'Quad-Widening Integer Multiply-Add'
Chih-Min Chao
14
-14
/
+35
2019-11-18
rvv: remove rest of vaadd_vi
Chih-Min Chao
1
-10
/
+0
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