Age | Commit message (Collapse) | Author | Files | Lines |
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* SFENCE.VMA requires S-mode
* MSTATUS.SUM hardwired to 0 if no S-Mode
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remove unecessary checking
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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include
1. unit-stride
2. strided
3. indexed
4. fault-first
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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for most instruction which are in
single, single, single/scalar/immediate format
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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include:
1. integer comparison
2. float comparison
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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include
1. narrow shift
2. narrow clip
3. wide mac
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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use 128bit to store temporary result to handle shift = 63 case in rv64
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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1. The rounding increment should be derived from the shift amount, not SEW.
2. Use 128bit to store temporary result to handle shift = 63 case in rv64
Signed-off-by: Albert Ou <aou@eecs.berkeley.edu>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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tail zero feature has been removed after v0.8-draft
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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don't use quiet api
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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has been removed in https://github.com/riscv/riscv-v-spec/pull/249
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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https://github.com/riscv/riscv-v-spec/commit/83fc27897b7b1fbc68e2e9e94f2ee05766315bac
https://github.com/riscv/riscv-v-spec/commit/fb40ef10f068827f3f0a926a83dd38ebcd470085
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In the previous scheme, debug-mode software could exit debug mode by
zeroing the dcsr.cause field. While benign, that behavior is out of
spec.
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based on v-spec 0.7.1, support
sections: 14/15.3 ~ 15.4
element size: 32
Signed-off-by: Bruce Hoult <bruce@hoult.org>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Dave Wen <dave.wen@sifive.com>
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based on v-spec 0.7.1, support
section: 7
element size: 8/16/32/64
Signed-off-by: Bruce Hoult <bruce@hoult.org>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Dave Wen <dave.wen@sifive.com>
Signed-off-by: Zakk Chen <zakk.chen@sifive.com>
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based on v-spec 0.7.1, support
sections: 12/13/15.1 ~ 15.2/16/17
element size: 8/16/32/64
support ediv: 1
Signed-off-by: Bruce Hoult <bruce@hoult.org>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Dave Wen <dave.wen@sifive.com>
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Signed-off-by: Bruce Hoult <bruce@hoult.org>
Signed-off-by: Dave Wen <dave.wen@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Previously, the exception would only be raised if the store-conditional
would have succeeded.
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- Use physical addresses to avoid homonym ambiguity (closes #215)
- Yield reservation on store-conditional (https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612)
- Don't yield reservation on exceptions (it's no longer required).
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See https://github.com/riscv/riscv-isa-manual/commit/01190b6ebeb29cfac6783a3e7ce30cd529bf6c59
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This mistake derives from an ambiguity in the specification that has since been corrected: https://github.com/riscv/riscv-isa-manual/commit/272d038abebe7f006ed7960b522f1e51890bb982
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Breaking out of the loop on WFI was intended to let other threads run
when the current thread has no work to do. There's no advantage to doing
so on CSR writes, and the unintentional change in thread interleaving
broke some test programs that relied on short timer periods.
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instructions encoded with zero shift amount"
This reverts commit be0555d585b332fd0496affe559c0a5a4e7e5644.
See #190
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encoded with zero shift amount
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See https://github.com/riscv/riscv-isa-manual/pull/139
Not adopted yet, but I'm putting the implementation here for reference.
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If rd=rs1 or rd=rs2, the NaN check examined the wrong value.
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https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ
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https://github.com/riscv/riscv-isa-manual/commit/f2ed45b1791bb602657adc2ea9ab5fc409c62542
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This improves simulator perf when a thread is idle, or waiting on HTIF.
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Resolves #76
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Resolves #88.
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