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2019-07-19Check vtype.vill for all vector instructions except vsetvl[i]Andrew Waterman23-13/+23
2019-07-19Check for F extension in vfmv instructionsAndrew Waterman2-0/+2
2019-07-19Avoid relying on sizeof longAndrew Waterman3-5/+5
2019-07-19vext.x.v -> vmv.x.s; unary operation encoding changesAndrew Waterman2-30/+25
https://github.com/riscv/riscv-v-spec/commit/83fc27897b7b1fbc68e2e9e94f2ee05766315bac https://github.com/riscv/riscv-v-spec/commit/fb40ef10f068827f3f0a926a83dd38ebcd470085
2019-07-12DRET should not be legal in M-modeAndrew Waterman1-1/+1
2019-07-12Add debug_mode state bit, rather than overloading dcsr.causeAndrew Waterman1-1/+1
In the previous scheme, debug-mode software could exit debug mode by zeroing the dcsr.cause field. While benign, that behavior is out of spec.
2019-07-05vmfirst/vmpopc have been renamed to vfirst/vpopcAndrew Waterman2-0/+0
2019-06-18rvv: add floating-point instructionsChih-Min Chao81-0/+509
based on v-spec 0.7.1, support sections: 14/15.3 ~ 15.4 element size: 32 Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Dave Wen <dave.wen@sifive.com>
2019-06-18rvv: add load/store instructionsChih-Min Chao44-0/+371
based on v-spec 0.7.1, support section: 7 element size: 8/16/32/64 Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Dave Wen <dave.wen@sifive.com> Signed-off-by: Zakk Chen <zakk.chen@sifive.com>
2019-06-18rvv: add integer/fixed-point/mask/reduction/permutation instructionsChih-Min Chao215-0/+2226
based on v-spec 0.7.1, support sections: 12/13/15.1 ~ 15.2/16/17 element size: 8/16/32/64 support ediv: 1 Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Dave Wen <dave.wen@sifive.com>
2019-06-18rvv: add control instructions and system register accessChih-Min Chao2-0/+2
Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Dave Wen <dave.wen@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2018-11-06Report misaligned-address exception on failed store-conditionalsAndrew Waterman2-14/+8
Previously, the exception would only be raised if the store-conditional would have succeeded.
2018-07-10Refactor and fix LR/SC implementation (#217)Andrew Waterman4-4/+8
- Use physical addresses to avoid homonym ambiguity (closes #215) - Yield reservation on store-conditional (https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612) - Don't yield reservation on exceptions (it's no longer required).
2018-05-04Revert "C.LWSP and C.LDSP with rd=0 are legal instructions"Andrew Waterman2-0/+2
See https://github.com/riscv/riscv-isa-manual/commit/01190b6ebeb29cfac6783a3e7ce30cd529bf6c59
2018-05-03C.LWSP and C.LDSP with rd=0 are legal instructionsAndrew Waterman2-2/+0
This mistake derives from an ambiguity in the specification that has since been corrected: https://github.com/riscv/riscv-isa-manual/commit/272d038abebe7f006ed7960b522f1e51890bb982
2018-04-30Only break out of the simulator loop on WFI, not on CSR writesAndrew Waterman1-1/+1
Breaking out of the loop on WFI was intended to let other threads run when the current thread has no work to do. There's no advantage to doing so on CSR writes, and the unintentional change in thread interleaving broke some test programs that relied on short timer periods.
2018-04-04Revert "Fix for issue #183: No illegal instruction exception for c.sxxi ↵Andrew Waterman3-3/+3
instructions encoded with zero shift amount" This reverts commit be0555d585b332fd0496affe559c0a5a4e7e5644. See #190
2018-03-16Fix for issue #183: No illegal instruction exception for c.sxxi instructions ↵Shubhodeep Roy Choudhury3-3/+3
encoded with zero shift amount
2018-03-03Implement clearing-misa.C-while-PC-is-misaligned proposalAndrew Waterman6-0/+6
See https://github.com/riscv/riscv-isa-manual/pull/139 Not adopted yet, but I'm putting the implementation here for reference.
2017-10-19Fix implementation of FMIN/FMAX NaN caseAndrew Waterman6-6/+12
If rd=rs1 or rd=rs2, the NaN check examined the wrong value.
2017-09-28Implement Q extensionAndrew Waterman40-8/+163
2017-06-30Remove reference to H-mode in ECALLAndrew Waterman1-1/+1
2017-05-25minNum -> minimumNumberAndrew Waterman4-8/+16
2017-05-13Make C.LI/C.LUI trapping behavior match specAndrew Waterman2-2/+1
2017-04-25FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.XAndrew Waterman2-0/+0
2017-04-10Implement new FP encodingAndrew Waterman54-62/+62
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ
2017-03-27On EBREAK, set badaddr to pcAndrew Waterman2-2/+2
2017-03-16Simplify interrupt-stack disciplineAndrew Waterman2-2/+2
https://github.com/riscv/riscv-isa-manual/commit/f2ed45b1791bb602657adc2ea9ab5fc409c62542
2017-03-13Implement mstatus.TW, mstatus.TVM, and mstatus.TSRAndrew Waterman3-2/+3
2017-02-20serialize simulator on wfiAndrew Waterman1-1/+1
This improves simulator perf when a thread is idle, or waiting on HTIF.
2017-02-15sfence.vm -> sfence.vmaAndrew Waterman1-0/+0
2017-02-01For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaNAndrew Waterman4-4/+12
Resolves #76
2017-02-01Set xPIE=1 on xRETAndrew Waterman2-2/+2
Resolves #88.
2016-11-10AMOs should always return store faults, not load faultsAndrew Waterman18-54/+18
This commit also factors out the common AMO code into mmu_t.
2016-08-17Allow mstatus.MPP to store bad values; instead, validate on MRETAndrew Waterman1-4/+1
Either approach is legal, but this more closely matches Rocket.
2016-07-28Add support for virtual priv register. (#59)Tim Newsome1-1/+4
Users can use this register to inspect and change the privilege level of the core. It doesn't make any assumptions about the actual underlying debug mechanism (as opposed to having the user change DCSR directly, which may not exist in all debug implementations).
2016-05-23Single step appears to work.Tim Newsome1-0/+3
2016-05-23Add dret.Tim Newsome2-3/+6
2016-05-23Properly save/restore dpc, mcause, mbadaddr.Tim Newsome1-0/+3
Also clear dcsr.cause when leaving Debug Mode so future traps go where they should.
2016-05-21Some bugfixes for CSR reading and setting FS for fflags updates (#43)Andy Wright4-8/+20
* csrrc[i] and csrrs[i] don't write CSRs if rs/zimm == 0 * Dirty fp state when setting new fp exceptions * Set FS to dirty for all non-zero fflags writes.
2016-04-19Split ERET into URET, SRET, HRET, MRETAndrew Waterman4-13/+15
2016-03-02Fix ERET bugAndrew Waterman1-1/+1
2016-03-02Serialize simulator on ERETAndrew Waterman1-2/+2
This guarantees interrupts will eventually be taken.
2016-03-02WIP on priv spec v1.9Andrew Waterman5-11/+11
2016-03-01Upgrade to latest SoftFloatAndrew Waterman48-52/+48
2015-11-19C.ADDIW is reserved for rd=0Andrew Waterman1-1/+2
2015-10-20Update to hopefully final RVC 1.9 encodingAndrew Waterman2-4/+0
2015-10-05more work towards RVC 1.8Andrew Waterman3-7/+7
2015-10-02work towards rvc 1.8Andrew Waterman20-13/+40
2015-10-02clean up shift instruction implementationAndrew Waterman4-22/+6
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