Age | Commit message (Expand) | Author | Files | Lines |
2017-03-16 | Simplify interrupt-stack discipline | Andrew Waterman | 2 | -2/+2 |
2017-03-13 | Implement mstatus.TW, mstatus.TVM, and mstatus.TSR | Andrew Waterman | 3 | -2/+3 |
2017-02-20 | serialize simulator on wfi | Andrew Waterman | 1 | -1/+1 |
2017-02-15 | sfence.vm -> sfence.vma | Andrew Waterman | 1 | -0/+0 |
2017-02-01 | For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN | Andrew Waterman | 4 | -4/+12 |
2017-02-01 | Set xPIE=1 on xRET | Andrew Waterman | 2 | -2/+2 |
2016-11-10 | AMOs should always return store faults, not load faults | Andrew Waterman | 18 | -54/+18 |
2016-08-17 | Allow mstatus.MPP to store bad values; instead, validate on MRET | Andrew Waterman | 1 | -4/+1 |
2016-07-28 | Add support for virtual priv register. (#59) | Tim Newsome | 1 | -1/+4 |
2016-05-23 | Single step appears to work. | Tim Newsome | 1 | -0/+3 |
2016-05-23 | Add dret. | Tim Newsome | 2 | -3/+6 |
2016-05-23 | Properly save/restore dpc, mcause, mbadaddr. | Tim Newsome | 1 | -0/+3 |
2016-05-21 | Some bugfixes for CSR reading and setting FS for fflags updates (#43) | Andy Wright | 4 | -8/+20 |
2016-04-19 | Split ERET into URET, SRET, HRET, MRET | Andrew Waterman | 4 | -13/+15 |
2016-03-02 | Fix ERET bug | Andrew Waterman | 1 | -1/+1 |
2016-03-02 | Serialize simulator on ERET | Andrew Waterman | 1 | -2/+2 |
2016-03-02 | WIP on priv spec v1.9 | Andrew Waterman | 5 | -11/+11 |
2016-03-01 | Upgrade to latest SoftFloat | Andrew Waterman | 48 | -52/+48 |
2015-11-19 | C.ADDIW is reserved for rd=0 | Andrew Waterman | 1 | -1/+2 |
2015-10-20 | Update to hopefully final RVC 1.9 encoding | Andrew Waterman | 2 | -4/+0 |
2015-10-05 | more work towards RVC 1.8 | Andrew Waterman | 3 | -7/+7 |
2015-10-02 | work towards rvc 1.8 | Andrew Waterman | 20 | -13/+40 |
2015-10-02 | clean up shift instruction implementation | Andrew Waterman | 4 | -22/+6 |
2015-09-15 | Zero-extend flw, fmv_s_x instructions | Christopher Celio | 2 | -2/+2 |
2015-09-08 | Improve instruction fetch | Andrew Waterman | 8 | -22/+20 |
2015-09-04 | Move towards RVC v1.8 | Andrew Waterman | 25 | -103/+57 |
2015-05-31 | Add rest of RV32C instructions | Andrew Waterman | 5 | -14/+68 |
2015-05-31 | Fix c.slliw implementation | Andrew Waterman | 1 | -1/+3 |
2015-05-31 | New RV64C proposal | Andrew Waterman | 24 | -17/+64 |
2015-05-31 | Take interrupts as soon as interrupts are enabled | Andrew Waterman | 2 | -6/+0 |
2015-05-09 | Upgrade to privileged architecture 1.7 | Andrew Waterman | 4 | -1/+10 |
2015-04-03 | Support setting ISA/subsets with --isa flag | Andrew Waterman | 152 | -22/+119 |
2015-04-02 | Simplify RV32 comparisons | Andrew Waterman | 10 | -10/+10 |
2015-03-30 | Implement RVC draft | Andrew Waterman | 22 | -8/+62 |
2015-03-17 | Merge [shm]call into ecall, [shm]ret into eret | Andrew Waterman | 5 | -8/+7 |
2015-03-12 | Use hcall instead of mcall | Andrew Waterman | 2 | -2/+3 |
2015-03-12 | Update to new privileged spec | Andrew Waterman | 57 | -63/+74 |
2015-02-08 | Use xlen, not xprlen, to refer to x-register width | Andrew Waterman | 17 | -26/+26 |
2015-01-02 | On misaligned fetch, set EPC to target, not branch itself | Andrew Waterman | 2 | -4/+5 |
2014-11-30 | Implement timer faithfully | Andrew Waterman | 6 | -6/+18 |
2014-11-22 | Revert "Enable support for the four custom instructions" | Yunsup Lee | 24 | -0/+0 |
2014-10-23 | Enable support for the four custom instructions | Arun Thomas | 24 | -0/+0 |
2014-09-27 | Avoid use of __int128_t | Andrew Waterman | 3 | -14/+6 |
2014-03-18 | Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETH | Andrew Waterman | 6 | -6/+6 |
2014-03-06 | Add fclass.{s|d} instructions | Andrew Waterman | 2 | -0/+4 |
2014-02-10 | Revert to old AUIPC definition | Andrew Waterman | 1 | -1/+1 |
2014-01-20 | Merge branch 'confprec' | Quan Nguyen | 33 | -0/+0 |
2013-12-09 | New RDCYCLE encoding | Andrew Waterman | 6 | -6/+6 |
2013-11-25 | Update to new privileged ISA | Andrew Waterman | 19 | -20/+17 |
2013-10-17 | Add empty opcode header files for half-precision | Quan Nguyen | 33 | -0/+0 |