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2020-05-18rvv: vid's mlen overlap checkingDave.Wen1-1/+1
2020-05-14rvv: add vzext/vsextChih-Min Chao6-0/+6
2020-05-13rvv: amo: fix wrong index eewChih-Min Chao27-27/+27
2020-05-13rvv: change to 0.9amoChih-Min Chao45-18/+72
2020-05-13rvv: amo pre-0.9Chih-Min Chao9-0/+18
2020-05-11rvv: change to 0.9 ldstChih-Min Chao75-204/+328
2020-05-07rvv: add eew and lmul for vle/vse/vleffDave.Wen1-1/+5
2020-05-04zfh: implementation all instructionsChih-Min Chao36-0/+167
2020-04-27rvv: commitlog: fix comparision dst informationChih-Min Chao2-2/+2
2020-04-24rvv: commitlog: fix missing informaiton for slide1Chih-Min Chao4-12/+12
2020-04-23rvv: fix vfncvt.xu.f.w for fp16Chih-Min Chao1-1/+1
2020-04-23rvv: aad fp16 support for vfwxxx.[wv]vChih-Min Chao9-0/+27
2020-04-22rvv: fix segment load/store nf checkingChih-Min Chao1-4/+4
2020-04-21rvv: fix vfmv for fp16Chih-Min Chao3-13/+36
2020-04-21rvv: fix vfmerge.vfm for fp16Chih-Min Chao1-2/+15
2020-04-21rvv: fix vfslide for fp16Chih-Min Chao2-0/+16
2020-04-21rvv: fix floating comparison for fp16Chih-Min Chao9-0/+27
2020-04-20rvv: refine vfncvt case for f32_to_[u]i16 casesChih-Min Chao3-6/+3
2020-04-20rvv: fix f16_to_[u]i16 conversionChih-Min Chao4-8/+4
2020-04-20rvv: remove debug messageChih-Min Chao1-1/+0
2020-04-19rvv: fix vfwredsum checking ruleChih-Min Chao1-1/+3
2020-04-16rvv: fix rtz cvtChih-Min Chao13-51/+47
2020-04-15rvv: add widen conversion instructionsChih-Min Chao7-51/+53
2020-04-15rvv: add narrow conversion instrucitonsChih-Min Chao6-42/+44
2020-04-15rvv: add normal and widen reduction instructionsChih-Min Chao6-12/+36
2020-04-15rvv: add vmfxx f16 compare instructionsChih-Min Chao10-0/+30
2020-04-15rvv: add .vf fp16 instructionsChih-Min Chao24-0/+76
2020-04-15rvv: add .vv fp16 instructionsChih-Min Chao21-0/+63
2020-04-14rvv: leave only SEW-bit segment storeChih-Min Chao16-151/+51
2020-04-14rvv: leave only sew-wise segment loadChih-Min Chao28-65/+64
2020-04-14rvv: add vfslide1[down|up].vf and refine checking ruleChih-Min Chao8-27/+62
2020-04-14rvv: add float conversion for rtz variantsChih-Min Chao6-0/+64
2020-04-10rvv: vslide[1]up now allows mask overlap when LMUL=1Chih-Min Chao3-3/+3
2020-04-05Don't acquire load reservation in the event of a faultAndrew Waterman2-2/+4
2020-04-05ebreak should write mtval with 0, not pcAndrew Waterman2-2/+2
2020-03-27rvv: fix int_max/min value calculationChih-Min Chao8-23/+26
2020-03-26rvv: fix vssraa.vi e64 corner caseChih-Min Chao1-1/+1
2020-03-24rvv: fix vmv reg checking failureChih-Min Chao3-1/+6
2020-03-23rvv: restrict segment load register ruleChih-Min Chao3-0/+3
2020-03-17rvv: fix vdiv corner caseChih-Min Chao2-2/+2
2020-03-12rvv: commitlog: fix vrgather_vv dumpChih-Min Chao1-4/+4
2020-03-12rvv: fix vfmv.f.s and vfmv.s.fChih-Min Chao2-22/+21
2020-03-11commitlog: fix missing dump for some instructionsChih-Min Chao7-25/+28
2020-03-11rvv: respect vstart and vl for vfmv.s.fChih-Min Chao1-19/+22
2020-03-05rvv: avoid redundant std::string comparisonZhen Wei2-13/+24
2020-03-05rvv: import parallel vf(w)redsum hardware impl.Zhen Wei4-14/+47
2020-03-03rvv: handle middle value of vslidedown.vxChih-Min Chao1-1/+1
2020-03-04rvv: remove the option of vector misaligned accessZhen Wei6-16/+16
2020-02-20Revert "rvv modify the vfredsum.vs behavior with e27 xlen=32"Max Lin1-54/+8
2020-02-20rvv modify the vfredsum.vs behavior with e27 xlen=32Max Lin1-8/+54
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