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2017-05-25minNum -> minimumNumberpriv-1.10Andrew Waterman4-8/+16
2017-05-13Make C.LI/C.LUI trapping behavior match specAndrew Waterman2-2/+1
2017-04-25FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.XAndrew Waterman2-0/+0
2017-04-10Implement new FP encodingAndrew Waterman54-62/+62
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ
2017-03-27On EBREAK, set badaddr to pcAndrew Waterman2-2/+2
2017-03-16Simplify interrupt-stack disciplineAndrew Waterman2-2/+2
https://github.com/riscv/riscv-isa-manual/commit/f2ed45b1791bb602657adc2ea9ab5fc409c62542
2017-03-13Implement mstatus.TW, mstatus.TVM, and mstatus.TSRAndrew Waterman3-2/+3
2017-02-20serialize simulator on wfiAndrew Waterman1-1/+1
This improves simulator perf when a thread is idle, or waiting on HTIF.
2017-02-15sfence.vm -> sfence.vmaAndrew Waterman1-0/+0
2017-02-01For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaNAndrew Waterman4-4/+12
Resolves #76
2017-02-01Set xPIE=1 on xRETAndrew Waterman2-2/+2
Resolves #88.
2016-11-10AMOs should always return store faults, not load faultsAndrew Waterman18-54/+18
This commit also factors out the common AMO code into mmu_t.
2016-08-17Allow mstatus.MPP to store bad values; instead, validate on MRETAndrew Waterman1-4/+1
Either approach is legal, but this more closely matches Rocket.
2016-07-28Add support for virtual priv register. (#59)Tim Newsome1-1/+4
Users can use this register to inspect and change the privilege level of the core. It doesn't make any assumptions about the actual underlying debug mechanism (as opposed to having the user change DCSR directly, which may not exist in all debug implementations).
2016-05-23Single step appears to work.Tim Newsome1-0/+3
2016-05-23Add dret.Tim Newsome2-3/+6
2016-05-23Properly save/restore dpc, mcause, mbadaddr.Tim Newsome1-0/+3
Also clear dcsr.cause when leaving Debug Mode so future traps go where they should.
2016-05-21Some bugfixes for CSR reading and setting FS for fflags updates (#43)Andy Wright4-8/+20
* csrrc[i] and csrrs[i] don't write CSRs if rs/zimm == 0 * Dirty fp state when setting new fp exceptions * Set FS to dirty for all non-zero fflags writes.
2016-04-19Split ERET into URET, SRET, HRET, MRETAndrew Waterman4-13/+15
2016-03-02Fix ERET bugAndrew Waterman1-1/+1
2016-03-02Serialize simulator on ERETAndrew Waterman1-2/+2
This guarantees interrupts will eventually be taken.
2016-03-02WIP on priv spec v1.9Andrew Waterman5-11/+11
2016-03-01Upgrade to latest SoftFloatAndrew Waterman48-52/+48
2015-11-19C.ADDIW is reserved for rd=0Andrew Waterman1-1/+2
2015-10-20Update to hopefully final RVC 1.9 encodingAndrew Waterman2-4/+0
2015-10-05more work towards RVC 1.8Andrew Waterman3-7/+7
2015-10-02work towards rvc 1.8Andrew Waterman20-13/+40
2015-10-02clean up shift instruction implementationAndrew Waterman4-22/+6
2015-09-15Zero-extend flw, fmv_s_x instructionsChristopher Celio2-2/+2
- This makes Spike more consistent with its zero-extending behavior regarding other SP operations when placed into the 64b f-registers.
2015-09-08Improve instruction fetchAndrew Waterman8-22/+20
- Performance for variable-length instructions is much better - Refill is simpler and faster - Support for instructions with overlapping opcodes (e.g. C.ADD + C.JALR)
2015-09-04Move towards RVC v1.8Andrew Waterman25-103/+57
2015-05-31Add rest of RV32C instructionsAndrew Waterman5-14/+68
2015-05-31Fix c.slliw implementationAndrew Waterman1-1/+3
2015-05-31New RV64C proposalAndrew Waterman24-17/+64
2015-05-31Take interrupts as soon as interrupts are enabledAndrew Waterman2-6/+0
Previously, if interrupts were enabled then disabled quickly enough, no interrupt would ever be taken, resulting in deadlock.
2015-05-09Upgrade to privileged architecture 1.7Andrew Waterman4-1/+10
2015-04-03Support setting ISA/subsets with --isa flagAndrew Waterman152-22/+119
Default is RV64IMAFDC. Can do things like --isa=RV32 (which implies IMAFDC) --isa=IM (which implies RV64) --isa=RV64IMAFDXhwacha
2015-04-02Simplify RV32 comparisonsAndrew Waterman10-10/+10
No need to eliminate the upper 32 bits of the 64-bit x-register, as all RV32 instructions should sign-extend their results to 64 bits.
2015-03-30Implement RVC draftAndrew Waterman22-8/+62
2015-03-17Merge [shm]call into ecall, [shm]ret into eretAndrew Waterman5-8/+7
2015-03-12Use hcall instead of mcallAndrew Waterman2-2/+3
2015-03-12Update to new privileged specAndrew Waterman57-63/+74
Sorry, everyone.
2015-02-08Use xlen, not xprlen, to refer to x-register widthAndrew Waterman17-26/+26
2015-01-02On misaligned fetch, set EPC to target, not branch itselfAndrew Waterman2-4/+5
2014-11-30Implement timer faithfullyAndrew Waterman6-6/+18
rdcycle/rdinstret now have single-instruction granularity. Questionable behavior when timer interrupts occurred around the same time as the compare register is written should be fixed.
2014-11-22Revert "Enable support for the four custom instructions"Yunsup Lee24-0/+0
This reverts commit fd18dc43f64d1938144f6c883ba4a2ca247611c6. Refactoring support for custom instructions.
2014-10-23Enable support for the four custom instructionsArun Thomas24-0/+0
* Update generated encoding.h (generated from riscv-opcodes) * Add empty implementations for the custom instructions
2014-09-27Avoid use of __int128_tAndrew Waterman3-14/+6
It is nonstandard, and GCC doesn't support it on 32-bit platforms. The resulting code for MULH[[S]U] is crappier, but that doesn't really matter, as these instructions are dynamically infrequent.
2014-03-18Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETHAndrew Waterman6-6/+6
2014-03-06Add fclass.{s|d} instructionsAndrew Waterman2-0/+4
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