| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
h/t @YenHaoChen
|
|
|
|
|
|
|
|
|
|
The Spike internals require that, when XLEN is narrower than reg_t,
values be sign-extended to the width of reg_t.
|
|
require_vector_novtype
|
|
|
|
|
|
|
|
|
|
Add space between ')' and '{'
|
|
instructions
change the extention check for F/D/Zfh instructions
modify the F/D/Zfh instructions to read X regs when enable Zfinx
Co-authored-by: wangmeng <shusheng8495@hotmail.com>
|
|
Before this commit Spike was requiring S mode privilege even without
S mode implemented. This commit fixes it.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
|
|
|
|
Now that logic only affects ebreak instructions, and does not affect
triggers that also cause a trap to be taken.
Fixes #725. Although like Paul, I don't have a test for this case.
Introduce trap_debug_mode so so ebreak instructions can force entry into
debug mode.
|
|
|
|
The alternative would be to #undef set_csr after including encoding.h,
but this solution strikes me as cleaner. Part of the reason is that
set_csr was not a great name: it sounds like it implements the CSRRS
(read & set) instruction, rather than impelementing a simple write.
|
|
'The instructions operate as if EEW=SEW.EMUL = NREG, effective length evl= EMUL * VLEN/SEW.'
So the start byte should take sew into acount when vstart != 0
|
|
This is a minor change, turning processor_t from a child class of
isa_parser_t into a class that contains an isa_parser_t as a field.
The point is that it is a step toward separating out
"configuration" (and ISA string parsing) from processor state. This
should be helpful for rejigging things so that we construct more from
a supplied device tree.
|
|
* perform hstatus probe/update for sret only when H extension enabled.
* added missing parenthesis
|
|
By spec 3.1.6.1 (original behavior)
"x PP is set to the least-privileged supported
mode (U if U-mode is implemented, else M)"
By spec 8.6.4 (h-extension)
"MRET first determines what the new privilege mode will be according to
the values of MPP and MPV in mstatus or mstatush, as encoded in Table 8.8.
MRET then in mstatus/mstatush sets MPV=0, MPP=0, MIE=MPIE, and
MPIE=1"
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
|
|
Before this patch, spike just had an "Xbitmanip" extension which
covered everything in the proposed bitmanip extension that hadn't been
ratified. The problem is that if you want to model (or verify) a
processor that targetted just some of the proposed bitmanip extension,
you couldn't configure Spike to do that.
For example, the lowRISC Ibex processor has several different
configurations. The "balanced" configuration targetted Zba, Zbb, Zbs,
Zbf and Zbt of the 0.92 spec. With the Zba, Zbb and Zbs ratified,
we'll now be able to use an ISA string like
rv32imc_Zba_Zbb_Zbs_XZbf_XZbt
and Spike will correctly fail to decode instructions like 'bcompress',
which would have been decoded with Xbitmanip.
This patch adds a new custom extension name for each part of the
extension that wasn't fully ratified. These have an 'X' prefix so, for
example, the bit permutation instructions that were proposed as Zbp
can be found under XZbp.
Specifying "Xbitmanip" gets all of these extensions, so its behaviour
should be unchanged.
Note that the slo(i) / sro(i) instructions have been moved from the
proposed Zbb to XZbp. This matches a comment in the Change History
section of v0.93 of the bitmanip spec: it seems that the authors
forgot to also move them in Table 2.1 (which gives the lists of
instructions for each extension). This change won't break anything
that currently exists, but it took quite a while to figure out what
was going on so I thought I'd leave a breadcrumb trail for the next
engineer!
The bulk of the patch is just defining some more entries in the
isa_extension_t enum and rewriting each of the instructions to depend
on the relevant entry. This is mostly a straight textual replacement
but it's slightly more complicated for things like the "pack"
instruction that are defined by several different proposed extensions.
|
|
prefetch.* are hints and share the encoding of ORI with rd = 0. so it can share the implementation of ORI and execute as no-ops
|
|
Refer to rvv-spec v1.0-rc2
|
|
Simplify float convert instructions
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Zfhmin is a subset of Zfh (half-precision IEEE 754 binary16 floating
point) extension, consisting only of data transfer and conversion
instructions.
This commit adds `EXT_ZFHMIN` to `isa_extension_t`, permits "zfhmin"
as a multi-letter extension and adjusts feature gate for
data transfer / conversion instructions.
* FLH / FSH
* FMV.X.H / FMV.H.X
* FCVT.S.H / FCVT.H.S
* FCVT.D.H / FCVT.H.D (if 'D' extension is also present)
* FCVT.Q.H / FCVT.H.Q (if 'Q' extension is also present)
|
|
Simply floating point parameters and merge operations
|
|
|
|
Simplify narrowing instruction
|
|
Leverage macro VI_WIDE_OP_AND_ASSIGN_MIX
|
|
|
|
|
|
|
|
|
|
|
|
This reverts commit 1a5b2d9dda8741e98444289135e0fbcb2c3f5740,
which is buggy (the vs1 argument is being sign-extended).
|
|
This allows them to share PARAM macro with narrowing right-shift instructions.
Rename VV_NSHIFT_PARAMS -> VV_NARROW_PARAMS so nclip, nsra, nsrl can share it.
(Same goes to VX_NSHIFT_PARAMS and VI_NSHIFT_PARAMS)
|
|
|
|
|
|
|
|
|
|
So I can fix breakpoints next to properly report gva.
|
|
Krypto 1.0 changes: Entropy source CSR, name.
List scalar crypto instruction groupings, as there is no single K extension.
Co-authored-by: Markku-Juhani O. Saarinen <mjos@mjos.fi>
|
