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2021-01-22scalar-crypto: Initial spike support for v0.8.1 (#635)Ben Marshall27-0/+698
2021-01-17rvb: add xperm.[nbhw] (#629)Chih-Min Chao4-0/+9
2021-01-08Update Zba/Zbb/Zbc to v0.93; Zbs/Zbe to v0.94-draftAndrew Waterman30-41/+11
2020-12-02rvv: index load/store have benn separated into ordered and unordered parts (#...Chih-Min Chao16-4/+13
2020-11-18Avoid use of __builtin_popcount for portabilityAndrew Waterman5-5/+5
2020-11-18Avoid use of __builtin_ctz for portabilityAndrew Waterman4-4/+4
2020-11-12Merge pull request #592 from scottj97/fix-misaligned-lrAndrew Waterman2-2/+2
2020-11-11mmu: check mmu supportChih-Min Chao1-0/+1
2020-11-11Make LR properly take misaligned exceptionScott Johnson2-2/+2
2020-10-22Merge pull request #580 from riscv/riscv-bitmanipAndrew Waterman105-0/+598
2020-10-22Remove subu.w; change addu.w definitionAndrew Waterman2-4/+1
2020-10-22[riscv-bitmanip] Add sh[123]add[u.w] instructionClifford Wolf6-0/+15
2020-10-22[riscv-bitmanip] Bugfixes in RV32B impl of CRC, SRO, [UN]SHFLClifford Wolf14-14/+14
2020-10-22[riscv-bitmanip] Changes for RISC-V Bitmanip Spec 0.92Clifford Wolf7-15/+29
2020-10-22[riscv-bitmanip] Changes for RISC-V Bitmanip Spec 0.91Clifford Wolf6-0/+62
2020-10-22[riscv-bitmanip] Add bitmanip instructionsClifford Wolf89-0/+510
2020-10-17fixed mtval update for breakpoint instructions (#573)Neel Gala2-2/+2
2020-09-24correctly respect mstatus.TW and hstatus.VTWAndrew Waterman1-2/+9
2020-09-24Correctly respect mstatus.TSRAndrew Waterman1-3/+6
2020-09-24Correctly respect mstatus.TVMAndrew Waterman2-4/+7
2020-09-24Fix priority of virtual vs. illegal instruction exceptions for HFENCEAndrew Waterman2-2/+2
2020-09-24Fix priority of virtual vs. illegal instruction exceptions for HLV/HSVAndrew Waterman13-13/+13
2020-09-22rvv: fix vfncvt/vfwcvt type checkingChih-Min Chao15-15/+165
2020-09-21Raise virtual-instruction traps correctly for WFI/SRET/SFENCEAndrew Waterman3-4/+6
2020-09-20Fix polarity of hstatus.HU fieldAndrew Waterman13-13/+13
2020-09-20Don't throw virtual instruction exceptions for unimplemented CSRsAndrew Waterman6-6/+6
2020-09-15rvv: fix int type is not enough to do shift (#544)Han-Kuan Chen2-2/+2
2020-09-15Populate tval registers on illegal-/virtual-instruction trapsAndrew Waterman6-6/+6
2020-08-31rvv: relax checking for vs1Chih-Min Chao2-2/+2
2020-08-31rvv: trigger exp for illegal ncvt/wcvt eewChih-Min Chao15-25/+24
2020-08-31rvv: check invalid frm for floating operationsChih-Min Chao2-0/+2
2020-08-31rvv: add reciprocal instructionsChih-Min Chao2-0/+22
2020-08-27rvv: remove quad instructionsChih-Min Chao7-35/+0
2020-08-20rvv: fix vrgatherei16 overlap ruleChih-Min Chao1-1/+2
2020-08-04Merge pull request #521 from chihminchao/op-hypvervisorAndrew Waterman1-2/+2
2020-08-03op: hyperviosr: fix exception code and nameChih-Min Chao1-2/+2
2020-08-03rvv: add 'vstartalu" option to --varch arugmentChih-Min Chao20-20/+20
2020-07-29rvv: add vrgatherei16.vvChih-Min Chao1-0/+33
2020-07-29rvv: add new whole reg load/store instructionsChih-Min Chao21-17/+39
2020-07-29rvv: op: fix amo namingChih-Min Chao36-0/+0
2020-07-15commitlog: fix vmvnfr.v register information (#506)Chih-Min Chao1-4/+17
2020-07-13rvv: fix viota.m dst and src overlapping rule (#504)Chih-Min Chao1-5/+1
2020-07-09Implement new instructions of hypervisor extensionAnup Patel15-0/+63
2020-07-09Implement hypervisor CSRs read/writeAnup Patel4-4/+19
2020-07-08Extend trap classes to pass more informationAnup Patel2-2/+2
2020-07-02rvv: make vmvfnr respect vstartChih-Min Chao1-5/+4
2020-06-25rvv: fix viota.m overlapping ruleChih-Min Chao1-1/+5
2020-06-17rvv: make v[sl]1r respect vstartChih-Min Chao2-2/+2
2020-06-16zfh: implement all instructionsChih-Min Chao36-0/+167
2020-06-15remove the redundant code (#488)Dave Wen1-1/+1
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