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rocket-tools/riscv-gnu-toolchain/spike.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
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Author
Files
Lines
2021-01-22
scalar-crypto: Initial spike support for v0.8.1 (#635)
Ben Marshall
27
-0
/
+698
2021-01-17
rvb: add xperm.[nbhw] (#629)
Chih-Min Chao
4
-0
/
+9
2021-01-08
Update Zba/Zbb/Zbc to v0.93; Zbs/Zbe to v0.94-draft
Andrew Waterman
30
-41
/
+11
2020-12-02
rvv: index load/store have benn separated into ordered and unordered parts (#...
Chih-Min Chao
16
-4
/
+13
2020-11-18
Avoid use of __builtin_popcount for portability
Andrew Waterman
5
-5
/
+5
2020-11-18
Avoid use of __builtin_ctz for portability
Andrew Waterman
4
-4
/
+4
2020-11-12
Merge pull request #592 from scottj97/fix-misaligned-lr
Andrew Waterman
2
-2
/
+2
2020-11-11
mmu: check mmu support
Chih-Min Chao
1
-0
/
+1
2020-11-11
Make LR properly take misaligned exception
Scott Johnson
2
-2
/
+2
2020-10-22
Merge pull request #580 from riscv/riscv-bitmanip
Andrew Waterman
105
-0
/
+598
2020-10-22
Remove subu.w; change addu.w definition
Andrew Waterman
2
-4
/
+1
2020-10-22
[riscv-bitmanip] Add sh[123]add[u.w] instruction
Clifford Wolf
6
-0
/
+15
2020-10-22
[riscv-bitmanip] Bugfixes in RV32B impl of CRC, SRO, [UN]SHFL
Clifford Wolf
14
-14
/
+14
2020-10-22
[riscv-bitmanip] Changes for RISC-V Bitmanip Spec 0.92
Clifford Wolf
7
-15
/
+29
2020-10-22
[riscv-bitmanip] Changes for RISC-V Bitmanip Spec 0.91
Clifford Wolf
6
-0
/
+62
2020-10-22
[riscv-bitmanip] Add bitmanip instructions
Clifford Wolf
89
-0
/
+510
2020-10-17
fixed mtval update for breakpoint instructions (#573)
Neel Gala
2
-2
/
+2
2020-09-24
correctly respect mstatus.TW and hstatus.VTW
Andrew Waterman
1
-2
/
+9
2020-09-24
Correctly respect mstatus.TSR
Andrew Waterman
1
-3
/
+6
2020-09-24
Correctly respect mstatus.TVM
Andrew Waterman
2
-4
/
+7
2020-09-24
Fix priority of virtual vs. illegal instruction exceptions for HFENCE
Andrew Waterman
2
-2
/
+2
2020-09-24
Fix priority of virtual vs. illegal instruction exceptions for HLV/HSV
Andrew Waterman
13
-13
/
+13
2020-09-22
rvv: fix vfncvt/vfwcvt type checking
Chih-Min Chao
15
-15
/
+165
2020-09-21
Raise virtual-instruction traps correctly for WFI/SRET/SFENCE
Andrew Waterman
3
-4
/
+6
2020-09-20
Fix polarity of hstatus.HU field
Andrew Waterman
13
-13
/
+13
2020-09-20
Don't throw virtual instruction exceptions for unimplemented CSRs
Andrew Waterman
6
-6
/
+6
2020-09-15
rvv: fix int type is not enough to do shift (#544)
Han-Kuan Chen
2
-2
/
+2
2020-09-15
Populate tval registers on illegal-/virtual-instruction traps
Andrew Waterman
6
-6
/
+6
2020-08-31
rvv: relax checking for vs1
Chih-Min Chao
2
-2
/
+2
2020-08-31
rvv: trigger exp for illegal ncvt/wcvt eew
Chih-Min Chao
15
-25
/
+24
2020-08-31
rvv: check invalid frm for floating operations
Chih-Min Chao
2
-0
/
+2
2020-08-31
rvv: add reciprocal instructions
Chih-Min Chao
2
-0
/
+22
2020-08-27
rvv: remove quad instructions
Chih-Min Chao
7
-35
/
+0
2020-08-20
rvv: fix vrgatherei16 overlap rule
Chih-Min Chao
1
-1
/
+2
2020-08-04
Merge pull request #521 from chihminchao/op-hypvervisor
Andrew Waterman
1
-2
/
+2
2020-08-03
op: hyperviosr: fix exception code and name
Chih-Min Chao
1
-2
/
+2
2020-08-03
rvv: add 'vstartalu" option to --varch arugment
Chih-Min Chao
20
-20
/
+20
2020-07-29
rvv: add vrgatherei16.vv
Chih-Min Chao
1
-0
/
+33
2020-07-29
rvv: add new whole reg load/store instructions
Chih-Min Chao
21
-17
/
+39
2020-07-29
rvv: op: fix amo naming
Chih-Min Chao
36
-0
/
+0
2020-07-15
commitlog: fix vmvnfr.v register information (#506)
Chih-Min Chao
1
-4
/
+17
2020-07-13
rvv: fix viota.m dst and src overlapping rule (#504)
Chih-Min Chao
1
-5
/
+1
2020-07-09
Implement new instructions of hypervisor extension
Anup Patel
15
-0
/
+63
2020-07-09
Implement hypervisor CSRs read/write
Anup Patel
4
-4
/
+19
2020-07-08
Extend trap classes to pass more information
Anup Patel
2
-2
/
+2
2020-07-02
rvv: make vmvfnr respect vstart
Chih-Min Chao
1
-5
/
+4
2020-06-25
rvv: fix viota.m overlapping rule
Chih-Min Chao
1
-1
/
+5
2020-06-17
rvv: make v[sl]1r respect vstart
Chih-Min Chao
2
-2
/
+2
2020-06-16
zfh: implement all instructions
Chih-Min Chao
36
-0
/
+167
2020-06-15
remove the redundant code (#488)
Dave Wen
1
-1
/
+1
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