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AgeCommit message (Expand)AuthorFilesLines
2011-04-15[sim] fixed jalr immediate bugAndrew Waterman1-2/+2
2011-04-12[xcc,pk,sim] added privileged cflush instructionAndrew Waterman1-0/+1
2011-04-12[xcc,sim] rvc loads and storesAndrew Waterman8-0/+20
2011-04-11[xcc,sim,opcodes] more rvc instructions and bug fixesAndrew Waterman4-2/+6
2011-04-09[sim] add vector traps to vector instructionsYunsup Lee43-0/+43
2011-04-09[sim] add vt stuffYunsup Lee43-0/+83
2011-04-09[xcc, sim] added rvc insn c.li; misc fixesAndrew Waterman1-0/+2
2011-04-09[xcc,pk,sim,opcodes] added first RVC instructionAndrew Waterman2-1/+2
2011-04-08[sim] fixed multiply-high in rv32Andrew Waterman2-2/+2
2011-04-05[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem in...Yunsup Lee36-0/+0
2011-04-04[opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)Yunsup Lee5-0/+0
2011-04-04[opcodes,pk,sim,xcc] add vector mem instructionsYunsup Lee30-0/+0
2011-04-04[opcodes,pk,sim,xcc] add stop,utidx instructionsYunsup Lee2-0/+0
2011-04-04[opcodes,pk,sim,xcc] add fence instructions for vector unitYunsup Lee4-0/+0
2011-03-30[xcc] fixed bug in amo{maxu,minu}.wAndrew Waterman2-2/+2
2011-03-25[sim,pk,xcc,opcodes] removed fminmag/fmaxmagAndrew Waterman4-24/+0
2011-03-25[xcc,pk,opcodes,sim] updated encoding/insn namesAndrew Waterman12-0/+43
2011-03-17[sim] LWU now illegal in RV32Andrew Waterman1-0/+1
2011-02-15[xcc,opcodes,pk,sim] krste's re-renaming spreeAndrew Waterman39-0/+0
2011-02-15[xcc,sim,opcodes] removed mtflh/mffl/mffhAndrew Waterman3-9/+0
2011-02-04[sim,pk] added interrupt-pending field to cause regAndrew Waterman1-1/+1
2011-02-02[sim,xcc,opcodes] added back mtflh.dAndrew Waterman2-4/+5
2011-02-01[xcc,opcodes,pk,sim] cleanup to FP ISAAndrew Waterman8-29/+10
2011-01-26[sim] changed divide-by-0 semanticsAndrew Waterman2-9/+8
2011-01-25[sim,opcodes] add mulhsu instructionAndrew Waterman1-0/+8
2011-01-25[opcodes,pk,sim,xcc] great renumbering of 2011, part deuxAndrew Waterman2-6/+0
2011-01-20[sim, pk, xcc, opcodes] great instruction renaming of 2011Andrew Waterman83-8/+14
2011-01-18[opcodes, sim, xcc] made *w insns illegal in RV32Andrew Waterman54-76/+113
2011-01-17[opcodes, pk, sim, xcc] removed nor, normalized macros to addiAndrew Waterman1-1/+0
2011-01-11[sim] fix jalr bugAndrew Waterman1-1/+1
2010-12-27[sim] fixed some compiler warningsAndrew Waterman4-4/+4
2010-12-27[sim] cleaned up handling of link registerAndrew Waterman1-1/+1
2010-11-21[sim] handle integer division overflowAndrew Waterman8-12/+32
2010-11-21[opcodes, pk, sim, xcc] Tweaked FP encodingAndrew Waterman64-116/+28
2010-11-21[pk] various PK cleanups/speedupsAndrew Waterman2-0/+2
2010-11-21[xcc, sim, pk, opcodes] new instruction encoding!Andrew Waterman165-166/+165
2010-11-21[xcc, sim, pk] link register is now x1Andrew Waterman1-1/+1
2010-10-26[sim] removed unnecessary trap in mfcr instructionAndrew Waterman1-3/+0
2010-10-26[sim,xcc] fixed minor bugs related to tp/cr29Andrew Waterman1-3/+0
2010-10-26[pk,sim,xcc] get rid of at register, introduce tp registerYunsup Lee2-4/+2
2010-10-25[sim,xcc,pk,opcodes] static rounding modes for FP insnsAndrew Waterman36-0/+124
2010-10-05[xcc,sim] eliminated vectored trapsAndrew Waterman2-2/+5
2010-10-02[sim, xcc] changed cvt/trunc to use GPRs for int argsAndrew Waterman16-16/+24
2010-10-02[xcc, sim] mff now uses rs2 for dataAndrew Waterman4-4/+4
2010-09-28[opcodes, sim, xcc] added mffl.d instructionAndrew Waterman1-0/+2
2010-09-23[xcc, sim] eliminated zero-extended immediatesAndrew Waterman3-3/+3
2010-09-22[sim] fixed bug in which shift operands were reversedAndrew Waterman6-6/+6
2010-09-20[xcc, sim] changed instruction format so imm12 subs for rs2Andrew Waterman143-191/+191
2010-09-13[xcc, sim] replaced ble/bleu with bge/bgeuAndrew Waterman4-4/+4
2010-09-12[sim] renamed sllv to sll (same for other shifts)Andrew Waterman6-0/+0
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