rocket-tools/riscv-gnu-toolchain/spike.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2022-08-01	WFI condition fix	Canberk Topal	1	-1/+3
	Before this commit Spike was requiring S mode privilege even without S mode implemented. This commit fixes it. Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
2021-09-08	Convert hstatus to csr_t family	Scott Johnson	1	-1/+1

2021-09-08	Convert mstatus into csr_t family	Scott Johnson	1	-1/+1
	Step 3 of plan described in csrs.h.
2020-09-24	correctly respect mstatus.TW and hstatus.VTW	Andrew Waterman	1	-2/+9

2020-09-21	Raise virtual-instruction traps correctly for WFI/SRET/SFENCE	Andrew Waterman	1	-2/+2

2020-07-09	Implement hypervisor CSRs read/write	Anup Patel	1	-0/+2
	We add newly defined hypervisor CSRs and allow M/HS-mode to access these CSRs. The MRET, SRET, ECALL and WFI instructions have also been updated so that virt-to-novirt switch and exception cause is based on HART virtualization state. Subsequent patches will implement two-stage page tables, HFENCE instructions and HSV/HLV instructions. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-04-30	Only break out of the simulator loop on WFI, not on CSR writes	Andrew Waterman	1	-1/+1
	Breaking out of the loop on WFI was intended to let other threads run when the current thread has no work to do. There's no advantage to doing so on CSR writes, and the unintentional change in thread interleaving broke some test programs that relied on short timer periods.
2017-03-13	Implement mstatus.TW, mstatus.TVM, and mstatus.TSR	Andrew Waterman	1	-0/+1

2017-02-20	serialize simulator on wfi	Andrew Waterman	1	-1/+1
	This improves simulator perf when a thread is idle, or waiting on HTIF.
2015-05-09	Upgrade to privileged architecture 1.7	Andrew Waterman	1	-0/+1