| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2019-06-04 | rvv: change vseq.?? to vmseq.?? and related insns | Chih-Min Chao | 1 | -7/+0 |
| 2019-05-19 | rvv: append 1950 check to unspported instruction | Chih-Min Chao | 1 | -0/+1 |
| 2019-04-25 | rvv: use the same naming conversion with vf | Chih-Min Chao | 1 | -1/+1 |
| 2019-04-17 | rvv: fix mask register position and width calculation | Chih-Min Chao | 1 | -2/+2 |
| 2019-04-17 | wip: changing the seq results into sew/lmul size element | Dave | 1 | -2/+3 |
| 2019-04-07 | rvv: testing WIP | Dave.Wen | 1 | -1/+1 |
| 2019-03-26 | update all instruction templates and part of the implementations | Dave.Wen | 1 | -2/+2 |
| 2019-03-26 | declare vector instructions without VFUNARY0/1 and VMUNARY0 | Dave.Wen | 1 | -0/+5 |
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index : rocket-tools/riscv-gnu-toolchain/spike.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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