rocket-tools/riscv-gnu-toolchain/spike.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2019-11-11	rvv: add register using check for wide and narrow insn	Chih-Min Chao	1	-1/+1
	include 1. narrow shift 2. narrow clip 3. wide mac Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11	rvv: fix the rounding bit position for vnclip instructions.	Albert Ou	1	-11/+6
	1. The rounding increment should be derived from the shift amount, not SEW. 2. Use 128bit to store temporary result to handle shift = 63 case in rv64 Signed-off-by: Albert Ou <aou@eecs.berkeley.edu> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-18	rvv: add integer/fixed-point/mask/reduction/permutation instructions	Chih-Min Chao	1	-0/+26
	based on v-spec 0.7.1, support sections: 12/13/15.1 ~ 15.2/16/17 element size: 8/16/32/64 support ediv: 1 Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Dave Wen <dave.wen@sifive.com>