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The Spike internals require that, when XLEN is narrower than reg_t,
values be sign-extended to the width of reg_t.
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Add space between ')' and '{'
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This is a minor change, turning processor_t from a child class of
isa_parser_t into a class that contains an isa_parser_t as a field.
The point is that it is a step toward separating out
"configuration" (and ISA string parsing) from processor state. This
should be helpful for rejigging things so that we construct more from
a supplied device tree.
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Adds commit log events for vstart to many vector instructions.
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except for load/store instructions
0 : all instruction can't have non-zero vstart
not 0 : all instruction can have non-zero vstart if it is not required
vstart must be zero in spec
the default value is 1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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vl in vmv.s.x
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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https://github.com/riscv/riscv-v-spec/commit/83fc27897b7b1fbc68e2e9e94f2ee05766315bac
https://github.com/riscv/riscv-v-spec/commit/fb40ef10f068827f3f0a926a83dd38ebcd470085
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