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path: root/riscv/insns/vmsif_m.h
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2022-08-10Add space between if/while/switch and '('Weiwei Li1-1/+1
Add space between ')' and '{'
2021-09-29Convert vl to csr_tScott Johnson1-1/+1
Adds commit log events for vl to many vector instructions.
2021-09-29Convert vstart to csr_tScott Johnson1-2/+2
Adds commit log events for vstart to many vector instructions.
2020-08-03rvv: add 'vstartalu" option to --varch arugmentChih-Min Chao1-1/+1
except for load/store instructions 0 : all instruction can't have non-zero vstart not 0 : all instruction can have non-zero vstart if it is not required vstart must be zero in spec the default value is 1 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-06-04rvv: fix vms[oib]f.m overlapping ruleChih-Min Chao1-3/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-28rvv: apply new overlapping and align macroChih-Min Chao1-2/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-28rvv: remove vmlenChih-Min Chao1-4/+3
vmlen has be changed to 1 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-14rvv: vms[bio]f.m need to start from 0Chih-Min Chao1-2/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-01-22commitlog: rvv: add commitlog support to misc instrutionsChih-Min Chao1-1/+1
other instructions, which doesn't use macro in decoder.h Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: remove configuable tail-zeroChih-Min Chao1-1/+0
tail zero feature has been removed after v0.8-draft Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-07-19Check vtype.vill for all vector instructions except vsetvl[i]Andrew Waterman1-1/+1
2019-06-18rvv: add integer/fixed-point/mask/reduction/permutation instructionsChih-Min Chao1-0/+34
based on v-spec 0.7.1, support sections: 12/13/15.1 ~ 15.2/16/17 element size: 8/16/32/64 support ediv: 1 Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Dave Wen <dave.wen@sifive.com>