rocket-tools/riscv-gnu-toolchain/spike.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2020-05-25	rvv: add e8 type for scale	Chih-Min Chao	1	-0/+1
	Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-24	rvv: support [u]i8 type	Chih-Min Chao	1	-0/+4
	Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-20	rvv: refine vfncvt case for f32_to_[u]i16 cases	Chih-Min Chao	1	-2/+1
	Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-16	rvv: fix rtz cvt	Chih-Min Chao	1	-2/+3
	Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-15	rvv: add narrow conversion instrucitons	Chih-Min Chao	1	-7/+7
	know issue: There is no f32_to_u[i]16 conversion function in softfloat. The implementation use f32_to_u[i]16 to work around and will be fixed after the related APIs are available miss f32_to_[u]i16 function Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-12	commitlog: rvv: add commitlog support to float instrunctions	Chih-Min Chao	1	-1/+1
	Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-01-13	rvv: vfncvt and vfwcvt need to check the widening support	Chih-Min Chao	1	-0/+3
	Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-12-12	rvv: fix vfwcvt/vfncvt for f32 -> f64 and f64 -> f32	Chih-Min Chao	1	-1/+2
	1. fix disam 2. refine checking rule and move them out of loop 3. add missing exception keeping for each element Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-27	rvv: rename vfncvt suffix and add rod rouding type	Chih-Min Chao	1	-0/+6
	1. vfncvt.v -> vfncvt.w 2. add vfncvt.rod.f.f.w Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>