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path: root/riscv/insns/vfmv_f_s.h
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2022-08-10Add space between if/while/switch and '('Weiwei Li1-1/+1
Add space between ')' and '{'
2021-09-29Convert vstart to csr_tScott Johnson1-1/+1
Adds commit log events for vstart to many vector instructions.
2021-09-27Convert frm & fflags to csr_tScott Johnson1-1/+1
Adds proper logging of fflags on FP arithmetic ops.
2021-09-08Rename supports_extension() to extension_enabled()Scott Johnson1-3/+3
Because this checks the dynamic run-time state of misa, let's use the same language as the misa spec (enabled vs disabled). Calling it supports_extension() could be confused for a check of the static configuration of Spike (i.e. the --isa string), which it was not.
2020-08-31rvv: check invalid frm for floating operationsChih-Min Chao1-0/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-03rvv: add 'vstartalu" option to --varch arugmentChih-Min Chao1-1/+1
except for load/store instructions 0 : all instruction can't have non-zero vstart not 0 : all instruction can have non-zero vstart if it is not required vstart must be zero in spec the default value is 1 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-04rvv: fp16: support element movement instructionsChih-Min Chao1-9/+16
vfmv/vfslide/vfmerge Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-12rvv: fix vfmv.s.f and vfmv.f.sChih-Min Chao1-0/+2
vfmv.s.f check valid vstart vfmv.f.s reset vstart in the end Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-01-09rvv: refinve vfmv to support float64Chih-Min Chao1-7/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: add reg checking for specifial instructionsChih-Min Chao1-1/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-07-19Check vtype.vill for all vector instructions except vsetvl[i]Andrew Waterman1-0/+1
2019-07-19Check for F extension in vfmv instructionsAndrew Waterman1-0/+1
2019-07-19Avoid relying on sizeof longAndrew Waterman1-1/+1
2019-06-18rvv: add floating-point instructionsChih-Min Chao1-0/+33
based on v-spec 0.7.1, support sections: 14/15.3 ~ 15.4 element size: 32 Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Dave Wen <dave.wen@sifive.com>