index
:
rocket-tools/riscv-gnu-toolchain/spike.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
riscv
/
insns
/
vfmacc_vf.h
Age
Commit message (
Expand
)
Author
Files
Lines
2020-04-15
rvv: add .vf fp16 instructions
Chih-Min Chao
1
-0
/
+3
2019-12-12
rvv: add vfxxx.vf float64 support
Chih-Min Chao
1
-0
/
+3
2019-06-12
rvv: move the common part into macro. except the funary00 and funary01
Dave.Wen
1
-9
/
+1
2019-06-08
rvv: reformat the code by 'astyle insns/v*.h -s2 -A2'
Dave
1
-1
/
+1
2019-06-04
rvv: change VFP_VF_LOOP to VI_VFP_VF_LOOP
Chih-Min Chao
1
-1
/
+1
2019-06-03
rvv: refactor to the VU
Dave.Wen
1
-1
/
+1
2019-04-30
rvv: decouple the vectorUnit to the processor's state.
Dave.Wen
1
-1
/
+1
2019-04-25
rvv: fix vfm* and vfnm
Chih-Min Chao
1
-11
/
+7
2019-03-28
rvv: add vf[n]macc_v[vf]
Dave.Wen
1
-3
/
+15
2019-02-22
implement some float opertions and vmv, no-op implementations for segmented l...
Bruce Hoult
1
-1
/
+1
2019-02-15
Rewrite vfmacc_vf to use macros
Bruce Hoult
1
-19
/
+5
2019-02-15
Add checking to vfmacc_vf
Bruce Hoult
1
-0
/
+3
2019-02-13
Fix bug in vfmacc_vf. RVV opcodes do not contain Rounding Mode field, use frm...
Bruce Hoult
1
-1
/
+1
2019-02-13
Update to 20190131 spec
Bruce Hoult
1
-0
/
+16