Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2015-03-12 | Update to new privileged spec | Andrew Waterman | 1 | -1/+1 | |
Sorry, everyone. | |||||
2013-09-27 | Use WRITE_RD/WRITE_FRD macros to write registers | Andrew Waterman | 1 | -1/+1 | |
2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+2 | |
2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -2/+0 | |
2011-01-18 | [opcodes, sim, xcc] made *w insns illegal in RV32 | Andrew Waterman | 1 | -0/+1 | |
now generic variants behave differently in RV32 and RV64. | |||||
2010-11-21 | [xcc, sim, pk, opcodes] new instruction encoding! | Andrew Waterman | 1 | -1/+1 | |
2010-09-22 | [sim] fixed bug in which shift operands were reversed | Andrew Waterman | 1 | -1/+1 | |
2010-09-20 | [xcc, sim] changed instruction format so imm12 subs for rs2 | Andrew Waterman | 1 | -1/+1 | |
2010-09-12 | [sim] renamed sllv to sll (same for other shifts) | Andrew Waterman | 1 | -0/+1 | |
2010-09-12 | [xcc, sim] moved shamt field and renamed shifts | Andrew Waterman | 1 | -1/+0 | |
2010-08-04 | [sim] Bug fixes in shifts, plus a new test case | Andrew Waterman | 1 | -1/+1 | |
2010-08-03 | [pk,sim,xcc] Renamed instructions to RISC-V spec | Andrew Waterman | 1 | -0/+1 | |
All word-sized arithmetic operations are now postfixed with 'w', and all double-word-sized arithmetic operations are no longer prefixed with 'd'. mtc0/mfc0 are removed and replaced with mfpcr/mtpcr/mwfpcr/mwtpcr. |