| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2015-04-02 | Simplify RV32 comparisons | Andrew Waterman | 1 | -1/+1 | |
| No need to eliminate the upper 32 bits of the 64-bit x-register, as all RV32 instructions should sign-extend their results to 64 bits. | |||||
| 2013-09-27 | Use WRITE_RD/WRITE_FRD macros to write registers | Andrew Waterman | 1 | -1/+1 | |
| 2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+1 | |
| 2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -1/+0 | |
| 2010-11-21 | [xcc, sim, pk, opcodes] new instruction encoding! | Andrew Waterman | 1 | -1/+1 | |
| 2010-09-20 | [xcc, sim] changed instruction format so imm12 subs for rs2 | Andrew Waterman | 1 | -1/+1 | |
| 2010-07-28 | [sim,xcc] Changed instruction format to RISC-V | Andrew Waterman | 1 | -1/+1 | |
| Massive changes to gcc, binutils to support new instruction encoding. Simulator reflects these changes. | |||||
| 2010-07-18 | Reorganized directory structure | Andrew Waterman | 1 | -0/+1 | |
| Moved cross-compiler to /xcc/ rather than / Added ISA sim in /sim/ Added Proxy Kernel in /pk/ (to be cleaned up) Added opcode map to /opcodes/ (ditto) Added documentation to /doc/ | |||||
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index : rocket-tools/riscv-gnu-toolchain/spike.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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