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Age	Commit message (Collapse)	Author	Files	Lines
2021-06-12	Revert the redundant check for lr instruction (#728)	sven	1	-1/+1
	Co-authored-by: zhongchengyong <zhongcy93@gmail.com>
2021-05-25	Add alignment check for lr instruction (#713)	sven	1	-1/+1
	Co-authored-by: zhongcy <zhongcy93@gmail.com>
2020-11-11	Make LR properly take misaligned exception	Scott Johnson	1	-1/+1
	Fixes https://github.com/riscv/riscv-isa-sim/issues/591
2020-03-23	Don't acquire load reservation in the event of a fault	Andrew Waterman	1	-1/+2
	I think this bug wasn't caught because OS code never steps over faulting LR instructions in practice. The exception is either fatal (in which case the point is moot) or the LR is re-executed (in which case the point is also moot). Resolves #431
2018-07-10	Refactor and fix LR/SC implementation (#217)	Andrew Waterman	1	-1/+1
	- Use physical addresses to avoid homonym ambiguity (closes #215) - Yield reservation on store-conditional (https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612) - Don't yield reservation on exceptions (it's no longer required).
2015-04-03	Support setting ISA/subsets with --isa flag	Andrew Waterman	1	-0/+1
	Default is RV64IMAFDC. Can do things like --isa=RV32 (which implies IMAFDC) --isa=IM (which implies RV64) --isa=RV64IMAFDXhwacha
2015-03-12	Update to new privileged spec	Andrew Waterman	1	-1/+1
	Sorry, everyone.
2013-09-27	Use WRITE_RD/WRITE_FRD macros to write registers	Andrew Waterman	1	-1/+1

2013-08-11	Instructions are no longer member functions	Andrew Waterman	1	-1/+2

2013-03-29	add load-reserved/store-conditional instructions	Andrew Waterman	1	-0/+2