| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2022-08-04 | Modify F/D/Zfh instructions to add support for Zfinx/Zdinx/Zhinx{min} ↵ | liweiwei | 1 | -6/+6 | |
| instructions change the extention check for F/D/Zfh instructions modify the F/D/Zfh instructions to read X regs when enable Zfinx Co-authored-by: wangmeng <shusheng8495@hotmail.com> | |||||
| 2017-10-19 | Fix implementation of FMIN/FMAX NaN case | Andrew Waterman | 1 | -1/+2 | |
| If rd=rs1 or rd=rs2, the NaN check examined the wrong value. | |||||
| 2017-05-25 | minNum -> minimumNumber | Andrew Waterman | 1 | -2/+4 | |
| 2017-04-10 | Implement new FP encoding | Andrew Waterman | 1 | -3/+3 | |
| https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ | |||||
| 2017-02-01 | For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN | Andrew Waterman | 1 | -1/+3 | |
| Resolves #76 | |||||
| 2016-03-01 | Upgrade to latest SoftFloat | Andrew Waterman | 1 | -2/+1 | |
| 2015-04-03 | Support setting ISA/subsets with --isa flag | Andrew Waterman | 1 | -0/+1 | |
| Default is RV64IMAFDC. Can do things like --isa=RV32 (which implies IMAFDC) --isa=IM (which implies RV64) --isa=RV64IMAFDXhwacha | |||||
| 2013-09-27 | Use WRITE_RD/WRITE_FRD macros to write registers | Andrew Waterman | 1 | -2/+2 | |
| 2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+4 | |
| 2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -4/+0 | |
| 2011-03-25 | [xcc,pk,opcodes,sim] updated encoding/insn names | Andrew Waterman | 1 | -0/+4 | |
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index : rocket-tools/riscv-gnu-toolchain/spike.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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