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path: root/riscv/insns/fcvt_s_wu.h
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2022-08-04Modify F/D/Zfh instructions to add support for Zfinx/Zdinx/Zhinx{min} ↵liweiwei1-2/+2
instructions change the extention check for F/D/Zfh instructions modify the F/D/Zfh instructions to read X regs when enable Zfinx Co-authored-by: wangmeng <shusheng8495@hotmail.com>
2017-04-10Implement new FP encodingAndrew Waterman1-1/+1
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ
2016-03-01Upgrade to latest SoftFloatAndrew Waterman1-1/+1
2015-04-03Support setting ISA/subsets with --isa flagAndrew Waterman1-0/+1
Default is RV64IMAFDC. Can do things like --isa=RV32 (which implies IMAFDC) --isa=IM (which implies RV64) --isa=RV64IMAFDXhwacha
2013-09-27Use WRITE_RD/WRITE_FRD macros to write registersAndrew Waterman1-1/+1
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+4
2011-06-12[sim] renamed to riscv-isa-runAndrew Waterman1-4/+0
2011-05-19[sim] more fp<->int fixesAndrew Waterman1-1/+1
2011-02-15[xcc,opcodes,pk,sim] krste's re-renaming spreeAndrew Waterman1-0/+4