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path: root/riscv/insns/divw.h
AgeCommit message (Expand)AuthorFilesLines
2015-04-03Support setting ISA/subsets with --isa flagAndrew Waterman1-0/+1
2015-03-12Update to new privileged specAndrew Waterman1-1/+1
2013-09-27Use WRITE_RD/WRITE_FRD macros to write registersAndrew Waterman1-2/+2
2012-02-15reimplement div[u][w]/rem[u][w]Andrew Waterman1-4/+4
2012-01-30fix divide by zero bugsYunsup Lee1-1/+1
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+7
2011-06-12[sim] renamed to riscv-isa-runAndrew Waterman1-7/+0
2011-04-23[sim] fixed divw/remw crashing simulatorAndrew Waterman1-3/+1
2011-04-16[sim] removed undefined behavior for non-canonical inputsAndrew Waterman1-1/+1
2011-01-26[sim] changed divide-by-0 semanticsAndrew Waterman1-2/+4
2011-01-18[opcodes, sim, xcc] made *w insns illegal in RV32Andrew Waterman1-3/+6
2010-12-27[sim] fixed some compiler warningsAndrew Waterman1-1/+1
2010-11-21[sim] handle integer division overflowAndrew Waterman1-2/+4
2010-11-21[xcc, sim, pk, opcodes] new instruction encoding!Andrew Waterman1-1/+1
2010-09-20[xcc, sim] changed instruction format so imm12 subs for rs2Andrew Waterman1-1/+1
2010-08-03[pk,sim,xcc] Renamed instructions to RISC-V specAndrew Waterman1-0/+2
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