| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2022-08-10 | Add space between if/while/switch and '(' | Weiwei Li | 1 | -1/+1 | |
| Add space between ')' and '{' | |||||
| 2015-04-03 | Support setting ISA/subsets with --isa flag | Andrew Waterman | 1 | -0/+1 | |
| Default is RV64IMAFDC. Can do things like --isa=RV32 (which implies IMAFDC) --isa=IM (which implies RV64) --isa=RV64IMAFDXhwacha | |||||
| 2015-02-08 | Use xlen, not xprlen, to refer to x-register width | Andrew Waterman | 1 | -3/+3 | |
| 2013-09-27 | Use WRITE_RD/WRITE_FRD macros to write registers | Andrew Waterman | 1 | -2/+2 | |
| 2012-02-15 | reimplement div[u][w]/rem[u][w] | Andrew Waterman | 1 | -2/+4 | |
| fixes bugs for inputs not properly sign-extended | |||||
| 2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+4 | |
| 2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -4/+0 | |
| 2011-04-16 | [sim] removed undefined behavior for non-canonical inputs | Andrew Waterman | 1 | -1/+1 | |
| 2011-01-18 | [opcodes, sim, xcc] made *w insns illegal in RV32 | Andrew Waterman | 1 | -2/+1 | |
| now generic variants behave differently in RV32 and RV64. | |||||
| 2010-11-21 | [sim] handle integer division overflow | Andrew Waterman | 1 | -1/+4 | |
| Behavior is now same as GCC's optimizer. Previously, we just crashed :) | |||||
| 2010-11-21 | [xcc, sim, pk, opcodes] new instruction encoding! | Andrew Waterman | 1 | -1/+1 | |
| 2010-09-20 | [xcc, sim] changed instruction format so imm12 subs for rs2 | Andrew Waterman | 1 | -1/+1 | |
| 2010-08-03 | [pk,sim,xcc] Renamed instructions to RISC-V spec | Andrew Waterman | 1 | -2/+2 | |
| All word-sized arithmetic operations are now postfixed with 'w', and all double-word-sized arithmetic operations are no longer prefixed with 'd'. mtc0/mfc0 are removed and replaced with mfpcr/mtpcr/mwfpcr/mwtpcr. | |||||
| 2010-07-28 | [sim,xcc] Changed instruction format to RISC-V | Andrew Waterman | 1 | -1/+1 | |
| Massive changes to gcc, binutils to support new instruction encoding. Simulator reflects these changes. | |||||
| 2010-07-18 | Reorganized directory structure | Andrew Waterman | 1 | -0/+2 | |
| Moved cross-compiler to /xcc/ rather than / Added ISA sim in /sim/ Added Proxy Kernel in /pk/ (to be cleaned up) Added opcode map to /opcodes/ (ditto) Added documentation to /doc/ | |||||
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index : rocket-tools/riscv-gnu-toolchain/spike.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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