aboutsummaryrefslogtreecommitdiff
path: root/riscv/insns/csrrw.h
AgeCommit message (Expand)AuthorFilesLines
2022-04-07Rename processor_t::set_csr to put_csr to fix build on RISC-VAndrew Waterman1-1/+1
2020-09-20Don't throw virtual instruction exceptions for unimplemented CSRsAndrew Waterman1-1/+1
2020-09-15Populate tval registers on illegal-/virtual-instruction trapsAndrew Waterman1-1/+1
2018-03-03Implement clearing-misa.C-while-PC-is-misaligned proposalAndrew Waterman1-0/+1
2015-03-12Update to new privileged specAndrew Waterman1-2/+2
2015-02-08Use xlen, not xprlen, to refer to x-register widthAndrew Waterman1-1/+1
2014-11-30Implement timer faithfullyAndrew Waterman1-1/+3
2014-03-18Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETHAndrew Waterman1-1/+1
2013-12-09New RDCYCLE encodingAndrew Waterman1-1/+1
2013-11-25Update to new privileged ISAAndrew Waterman1-0/+2