Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2019-06-14 | rvv: fix indent | Chih-Min Chao | 1 | -1/+1 |
2019-06-12 | rvv: merge the vcsr to ordinary csr and remove the redundant functions | Dave.Wen | 1 | -10/+2 |
2019-06-03 | rvv: refactor to the VU | Dave.Wen | 1 | -2/+2 |
2019-04-30 | rvv: decouple the vectorUnit to the processor's state. | Dave.Wen | 1 | -2/+2 |
2019-04-20 | add csrr[csw]i | Dave | 1 | -3/+11 |
2018-03-03 | Implement clearing-misa.C-while-PC-is-misaligned proposal | Andrew Waterman | 1 | -0/+1 |
2016-05-21 | Some bugfixes for CSR reading and setting FS for fflags updates (#43) | Andy Wright | 1 | -2/+5 |
2015-03-12 | Update to new privileged spec | Andrew Waterman | 1 | -2/+2 |
2015-02-08 | Use xlen, not xprlen, to refer to x-register width | Andrew Waterman | 1 | -1/+1 |
2014-11-30 | Implement timer faithfully | Andrew Waterman | 1 | -1/+3 |
2014-03-18 | Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETH | Andrew Waterman | 1 | -1/+1 |
2013-12-09 | New RDCYCLE encoding | Andrew Waterman | 1 | -1/+1 |
2013-11-25 | Update to new privileged ISA | Andrew Waterman | 1 | -0/+2 |