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path: root/riscv/insns/csrrs.h
AgeCommit message (Expand)AuthorFilesLines
2019-06-12rvv: merge the vcsr to ordinary csr and remove the redundant functionsDave.Wen1-11/+3
2019-06-03rvv: refactor to the VUDave.Wen1-2/+2
2019-04-30rvv: decouple the vectorUnit to the processor's state.Dave.Wen1-2/+2
2019-04-18fix the vcsr write statementDave.Wen1-4/+6
2019-04-18rvv: support programming vcsrDave.Wen1-1/+7
2018-03-03Implement clearing-misa.C-while-PC-is-misaligned proposalAndrew Waterman1-0/+1
2016-05-21Some bugfixes for CSR reading and setting FS for fflags updates (#43)Andy Wright1-2/+5
2015-03-12Update to new privileged specAndrew Waterman1-2/+2
2015-02-08Use xlen, not xprlen, to refer to x-register widthAndrew Waterman1-1/+1
2014-11-30Implement timer faithfullyAndrew Waterman1-1/+3
2014-03-18Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETHAndrew Waterman1-1/+1
2013-12-09New RDCYCLE encodingAndrew Waterman1-1/+1
2013-11-25Update to new privileged ISAAndrew Waterman1-0/+2