Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2018-05-04 | Revert "C.LWSP and C.LDSP with rd=0 are legal instructions" | Andrew Waterman | 1 | -0/+1 | |
See https://github.com/riscv/riscv-isa-manual/commit/01190b6ebeb29cfac6783a3e7ce30cd529bf6c59 | |||||
2018-05-03 | C.LWSP and C.LDSP with rd=0 are legal instructions | Andrew Waterman | 1 | -1/+0 | |
This mistake derives from an ambiguity in the specification that has since been corrected: https://github.com/riscv/riscv-isa-manual/commit/272d038abebe7f006ed7960b522f1e51890bb982 | |||||
2015-05-31 | New RV64C proposal | Andrew Waterman | 1 | -0/+1 | |
2015-04-03 | Support setting ISA/subsets with --isa flag | Andrew Waterman | 1 | -1/+1 | |
Default is RV64IMAFDC. Can do things like --isa=RV32 (which implies IMAFDC) --isa=IM (which implies RV64) --isa=RV64IMAFDXhwacha | |||||
2015-03-30 | Implement RVC draft | Andrew Waterman | 1 | -0/+2 | |
2013-07-26 | Rip out RVC for now | Andrew Waterman | 1 | -2/+0 | |
2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+2 | |
2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -2/+0 | |
2011-04-12 | [xcc,sim] rvc loads and stores | Andrew Waterman | 1 | -0/+2 | |