| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2022-08-10 | Add space between if/while/switch and '(' | Weiwei Li | 1 | -1/+1 | |
| Add space between ')' and '{' | |||||
| 2015-04-02 | Simplify RV32 comparisons | Andrew Waterman | 1 | -1/+1 | |
| No need to eliminate the upper 32 bits of the 64-bit x-register, as all RV32 instructions should sign-extend their results to 64 bits. | |||||
| 2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+2 | |
| 2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -2/+0 | |
| 2011-06-11 | [xcc] instructions now set PC explicitly | Andrew Waterman | 1 | -1/+1 | |
| 2010-09-20 | [xcc, sim] changed instruction format so imm12 subs for rs2 | Andrew Waterman | 1 | -1/+1 | |
| 2010-09-13 | [xcc, sim] replaced ble/bleu with bge/bgeu | Andrew Waterman | 1 | -0/+2 | |
| This will simplify control logic (since every branch has a logical inverse) | |||||
 |
index : rocket-tools/riscv-gnu-toolchain/spike.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
| aboutsummaryrefslogtreecommitdiff |