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2020-05-14rvv: op: reorder vextChih-Min Chao1-18/+18
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-13rvv: change to 0.9amoChih-Min Chao1-54/+108
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-12rvv: add ext opcodeChih-Min Chao1-0/+18
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-12rvv: op: change vfunary0 and funary1 func6 fieldChih-Min Chao1-47/+47
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-11rvv: change to 0.9 ldstChih-Min Chao1-134/+195
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-04zfh: op: add scalar opcodeChih-Min Chao1-0/+108
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-14rvv: add vfslide1[down|up].vf and refine checking ruleChih-Min Chao1-0/+6
new features in spec 0.9 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-14rvv: add float conversion for rtz variantsChih-Min Chao1-0/+18
new features in spec 0.9 ref: https://github.com/riscv/riscv-v-spec/issues/352 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-14rvv: add new vcsr vector csrChih-Min Chao1-0/+2
new features in spec 0.9 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-10op: update CSRChih-Min Chao1-2/+28
1. add new hypervisor csr 2. add debug module csr 3. add some new high part register for rv32 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-03op: update encodingChih-Min Chao1-315/+372
change to 0ce3ec1 1. mstatus.vs is changed 2. opcodes are separated into difference files by extensions. The opcodes are not modifed but order are differenct. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-03Add do-nothing support for mcountinhibit CSRRupert Swarbrick1-0/+2
This CSR appeared in version 1.11 of the ISA and is described in the Volume II: Privileged Architecture manual. It's an optional register and should read as zero if not implemented, which is what this patch does.
2020-01-06rvv : vmv[1248]r.vChih-Min Chao1-0/+12
simple register copy instructions Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-12-02rvv: support new mstatus.vs field defined in v0.8Chih-Min Chao1-0/+2
mstatus.vs is similiar to mstatus.fs and used to contoller the state of vector unit. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-27rvv: replace vn suffic by 'w'Chih-Min Chao1-36/+36
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-27rvv: add load/store whole registerChih-Min Chao1-0/+6
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-27rvv: rename vfncvt suffix and add rod rouding typeChih-Min Chao1-18/+18
1. vfncvt*.v -> vfncvt*.w 2. add vfncvt.rod.f.f.w Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-27rvv: add quad insn and new vlenb csrChih-Min Chao1-21/+23
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-17Re-encode vaadd/vasub; remove vaadd.vi; add vaaddu/vasubuAndrew Waterman1-43/+55
2019-10-22rvv: remove vmfordChih-Min Chao1-6/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-10-14rvv: update encoding to v0.8Chih-Min Chao1-12/+12
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-09-05rvv: change vext to vmvChih-Min Chao1-3/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-09-05Revert "vext.x.v -> vmv.x.s; unary operation encoding changes"Chih-Min Chao1-13/+13
This reverts commit f36b73e4741e42bf5786cbac0bf022f1e9bfe309. to makeh 0.7.2-0616-draft
2019-09-04vext.x.v -> vmv.x.s; unary operation encoding changesAndrew Waterman1-13/+13
https://github.com/riscv/riscv-v-spec/commit/83fc27897b7b1fbc68e2e9e94f2ee05766315bac https://github.com/riscv/riscv-v-spec/commit/fb40ef10f068827f3f0a926a83dd38ebcd470085
2019-09-04vmfirst/vmpopc have been renamed to vfirst/vpopcAndrew Waterman1-32/+43
2019-06-13rvv: separte vfunary0 into independent instructionsChih-Min Chao1-3/+42
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-13rvv: spearate vfunary1 into independent instructionsChih-Min Chao1-3/+6
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-06rvv: follow new instruction name changeChih-Min Chao1-36/+30
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-05rvv: fix vmerge.vim/vmv.v.i encodingChih-Min Chao1-2/+2
also remove duplicated extension Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-04rvv: sepapate vfmergeChih-Min Chao1-3/+6
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-04rvv: move vadc/vsbc.v[vxi] to vadc/vsbc.v[vxi]mChih-Min Chao1-15/+30
also add vmsdc/vmadc encoding/disasm Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-04rvv: separate vmerge and vmvChih-Min Chao1-9/+18
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-04rvv: fix vs2 to v0Chih-Min Chao1-2/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-04rvv: vmiota_m -> viota_mChih-Min Chao1-3/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-04rvv: change vseq.?? to vmseq.?? and related insnsChih-Min Chao1-60/+60
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-04rvv: add vfrsub.vfChih-Min Chao1-0/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-04rvv: add amo encodingChih-Min Chao1-0/+81
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-04rvv: change vfeq to vmfeq and related comparision instructionChih-Min Chao1-36/+36
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-05-29rvv: add fault-first load segment encondingChih-Min Chao1-7/+7
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-05-20rvv: change viota_m to vmiota_mChih-Min Chao1-3/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-05-19rvv: separate vmuary0 by new encoding changeChih-Min Chao1-21/+33
follow riscv-opcode 7ebe3a7 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-05-16rvv: fix integer reduction instruction suffixChih-Min Chao1-24/+24
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-05-13rvv: update encodingChih-Min Chao1-4/+32
1. rebase to master 2. refine vsux don't support segment Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-05-13Revert "Add FLH and FSH instructions expanding IEEE fp16 in memory to fp32 ↵Chih-Min Chao1-6/+0
in registers" this is experimental implementation This reverts commit f04f29d352d413d2bc1ed1c7f60319461746540a. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-04-24rvv: fix sign-injection namingChih-Min Chao1-12/+12
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-04-18rvv: add CSR encodingDave.Wen1-0/+10
2019-04-02rvv: fix encoding namingChih-Min Chao1-18/+18
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-03-26rvv: update decoding header for vector extensionChih-Min Chao1-64/+915
include all valu/vmem instructions Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-03-26rvv: merge vssseg[3-6]w.v into vssw.vChih-Min Chao1-22/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-03-26rvv: merge vlsseg[3-6]w.v into vlsw.vChih-Min Chao1-22/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
generated by cgit v1.1 at 2024-09-12 02:31:16 +0000