aboutsummaryrefslogtreecommitdiff
path: root/riscv/encoding.h
AgeCommit message (Expand)AuthorFilesLines
2020-05-14rvv: op: reorder vextChih-Min Chao1-18/+18
2020-05-13rvv: change to 0.9amoChih-Min Chao1-54/+108
2020-05-12rvv: add ext opcodeChih-Min Chao1-0/+18
2020-05-12rvv: op: change vfunary0 and funary1 func6 fieldChih-Min Chao1-47/+47
2020-05-11rvv: change to 0.9 ldstChih-Min Chao1-134/+195
2020-05-04zfh: op: add scalar opcodeChih-Min Chao1-0/+108
2020-04-14rvv: add vfslide1[down|up].vf and refine checking ruleChih-Min Chao1-0/+6
2020-04-14rvv: add float conversion for rtz variantsChih-Min Chao1-0/+18
2020-04-14rvv: add new vcsr vector csrChih-Min Chao1-0/+2
2020-04-10op: update CSRChih-Min Chao1-2/+28
2020-03-03op: update encodingChih-Min Chao1-315/+372
2020-03-03Add do-nothing support for mcountinhibit CSRRupert Swarbrick1-0/+2
2020-01-06rvv : vmv[1248]r.vChih-Min Chao1-0/+12
2019-12-02rvv: support new mstatus.vs field defined in v0.8Chih-Min Chao1-0/+2
2019-11-27rvv: replace vn suffic by 'w'Chih-Min Chao1-36/+36
2019-11-27rvv: add load/store whole registerChih-Min Chao1-0/+6
2019-11-27rvv: rename vfncvt suffix and add rod rouding typeChih-Min Chao1-18/+18
2019-11-27rvv: add quad insn and new vlenb csrChih-Min Chao1-21/+23
2019-11-17Re-encode vaadd/vasub; remove vaadd.vi; add vaaddu/vasubuAndrew Waterman1-43/+55
2019-10-22rvv: remove vmfordChih-Min Chao1-6/+0
2019-10-14rvv: update encoding to v0.8Chih-Min Chao1-12/+12
2019-09-05rvv: change vext to vmvChih-Min Chao1-3/+3
2019-09-05Revert "vext.x.v -> vmv.x.s; unary operation encoding changes"Chih-Min Chao1-13/+13
2019-09-04vext.x.v -> vmv.x.s; unary operation encoding changesAndrew Waterman1-13/+13
2019-09-04vmfirst/vmpopc have been renamed to vfirst/vpopcAndrew Waterman1-32/+43
2019-06-13rvv: separte vfunary0 into independent instructionsChih-Min Chao1-3/+42
2019-06-13rvv: spearate vfunary1 into independent instructionsChih-Min Chao1-3/+6
2019-06-06rvv: follow new instruction name changeChih-Min Chao1-36/+30
2019-06-05rvv: fix vmerge.vim/vmv.v.i encodingChih-Min Chao1-2/+2
2019-06-04rvv: sepapate vfmergeChih-Min Chao1-3/+6
2019-06-04rvv: move vadc/vsbc.v[vxi] to vadc/vsbc.v[vxi]mChih-Min Chao1-15/+30
2019-06-04rvv: separate vmerge and vmvChih-Min Chao1-9/+18
2019-06-04rvv: fix vs2 to v0Chih-Min Chao1-2/+2
2019-06-04rvv: vmiota_m -> viota_mChih-Min Chao1-3/+3
2019-06-04rvv: change vseq.?? to vmseq.?? and related insnsChih-Min Chao1-60/+60
2019-06-04rvv: add vfrsub.vfChih-Min Chao1-0/+3
2019-06-04rvv: add amo encodingChih-Min Chao1-0/+81
2019-06-04rvv: change vfeq to vmfeq and related comparision instructionChih-Min Chao1-36/+36
2019-05-29rvv: add fault-first load segment encondingChih-Min Chao1-7/+7
2019-05-20rvv: change viota_m to vmiota_mChih-Min Chao1-3/+3
2019-05-19rvv: separate vmuary0 by new encoding changeChih-Min Chao1-21/+33
2019-05-16rvv: fix integer reduction instruction suffixChih-Min Chao1-24/+24
2019-05-13rvv: update encodingChih-Min Chao1-4/+32
2019-05-13Revert "Add FLH and FSH instructions expanding IEEE fp16 in memory to fp32 in...Chih-Min Chao1-6/+0
2019-04-24rvv: fix sign-injection namingChih-Min Chao1-12/+12
2019-04-18rvv: add CSR encodingDave.Wen1-0/+10
2019-04-02rvv: fix encoding namingChih-Min Chao1-18/+18
2019-03-26rvv: update decoding header for vector extensionChih-Min Chao1-64/+915
2019-03-26rvv: merge vssseg[3-6]w.v into vssw.vChih-Min Chao1-22/+1
2019-03-26rvv: merge vlsseg[3-6]w.v into vlsw.vChih-Min Chao1-22/+1
generated by cgit v1.1 at 2024-07-11 06:27:54 +0000