rocket-tools/riscv-gnu-toolchain/spike.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2019-10-08	Speed up compilation of disasm.cc, especially in clang	Andrew Waterman	1	-2/+2

2019-06-09	rvv: fix indent	Chih-Min Chao	1	-1/+1
	Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-05-09	Add a tool "spike-log-parser" to get the instruction name from spike log.	Jerry Shih	1	-1/+9
	Usage: ./spike-log-parser < $(log_file) Here is the example log: x15 a5 <- 0x000000008004935e 2147783518 core 0: 0x000000008000c362 (0xca278793) addi a5, a5, -862 x15 a5 <- 0x0000000080049000 2147782656 core 0: 0x000000008000c366 (0x0000639c) c.ld a5, 0(a5) x15 a5 <- 0x0000000000000000 0 core 0: 0x000000008000c368 (0xfef43423) sd a5, -24(s0) The output will be: addi c.ld sd
2019-04-17	disasm: make instruction name dynamic	Chih-Min Chao	1	-1/+2
	to support not const instruction name generated by generated string Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-02-24	typo in vector disassembly	Bruce Hoult	1	-1/+1

2019-02-24	Add ability for disassembler to have instructions with optional arguments	Bruce Hoult	1	-3/+22

2018-03-26	Add an api to get the name for a CSR.	Prashanth Mundkur	1	-0/+1

2016-06-29	Disassemble RVC instructions based on XLEN	Andrew Waterman	1	-3/+3
	The interpretation of RVC opcodes depends on XLEN, and the disassembler always assumed RV32. h/t Michael Clark
2014-09-27	Avoid some unused variable warnings	Andrew Waterman	1	-13/+2
	...and also save some space by not defining the register names in a header.
2014-07-24	added support for register convention names in debug mode	Scott Beamer	1	-0/+14

2013-10-18	refactor disassembler, and add hwacha disassembler	Yunsup Lee	1	-5/+50

2013-03-25	add BSD license	Andrew Waterman	1	-0/+2

2011-11-11	Remove dependence on binutils	Your Name	1	-0/+23
	We now have our own disassembler.